SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
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www.acromag.com
The Interrupt Status register at the carrier’s base a offset
0x0000_3000 is used to monitor pending interrupts corresponding to all
interrupting channels. For example, channel 0 is monitored via data bit-0.
Interrupt Polarity Registers (Read/Write) - (BAR1 + 0x0000 0018)
APZU-301 (28 Channels)
APZU-303 (20 Channels)
APZU-304 (14 Channels)
The Interrupt Polarity Register determines the level that will cause a channel
interrupt to occur for each of the channels enabled for level interrupts. A
“0” bit specifies that an interrupt will occur when the corresponding input
channel is low (i.e. a “0” in the digital input channel data register). A “1” bit
means that an interrupt will occur when the input channel is high (i.e. a “1”
in the digital input channel data register). Note that no interrupts will occur
unless they are enabled by the Interrupt Enable Register. Further, the
Interrupt Polarity Register will have no effect if the Change-of-State (COS)
interrupt type is configured by the Interrupt Type Configuration Register.
The Interrupt Polarity register at the carrier’s base a offset
0x0000_0018 is used to control the individual channel polarity. For
example, channel 0 is controlled via data bit-0.
All bits are set to “0” following a reset which means that the inputs will
cause interrupts when they are below logic low threshold (provided they are
enabled for interrupt on level).
Interrupt Status Register (Read/Write) - (BAR1 + 0x0000 001C)
RS485 Data Registers (Read/Write) - (BAR1 + 0x0000 002C)
APZU-303 only
Three possible input/output channels numbered 0 through 2 may be
individually accessed via these registers. The RS485 Data register is used to
monitor/read or set/write channels 0 through 2. Channels 0 to 2 are
accessed at the carrier base a 0000_002C via data bits 0 to 2.
APZU-301 (28 Channels)
APZU-303 (20 Channels)
APZU-304 (14 Channels)
The Interrupt Status Register reflects the status of each of the interrupt
channels. A “1” bit indicates that an interrupt is pending for the
corresponding channel. A channel that does not have interrupts enabled
will never set its interrupt status flag. A channel’s interrupt can be cleared
by writing a “1” to its bit position in the Interrupt Status Register (writing a
“1” acts as a reset signal to clear the set state). However, if the condition
which caused the interrupt to occur remains, the interrupt will be generated
again (unless disabled via the Interrupt Enable Register).
Note that the input channel bandwidth should be limited to reduce the
possibility of missing channel interrupts. For a specific input channel, this
could happen if multiple changes occur before the channel’s interrupt is
serviced.
All interrupts are cleared following a reset.
