SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
34
-
www.acromag.com
The current project contains the Acromag example design. To access the
ARM processing system, we open the block design of the Vivado project
using IP Integrator.
Select =>
Open Block Design
The top level block diagram of the example design is shown in the Figure
below. This view shows the AXI interfaces link together the Zynq Ult
MPSoC, System Management Wizard, Block Memory Generator, and the
M01_AXI. The M01_AXI interface connects to the Acromag custom VHDL
code.
The M01_AXI, AXI_ACLK, AXI_RESETn signals are brought out with the
Create HDL Wrapper to the top level VHD file APZU_top.vhd. The M01_AXI
interface is used to control the digital I/O signals of the module.
The AXI interconnect IP is configured with one slave interfaces and three
master interfaces. The slave interfaces link to the Zynq Ult MPSoC.
The three slave interfaces connect to the Block Memory, System
Management Wizard, and M01_AXI interface to the APZU_top.vhd top level
design.
