SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
43
-
www.acromag.com
If changes involved the addition or removal of signals between the block
design and the top level design you will need to update the HDL wrapper.
Right click Your Design_1.bd. Then select
Create HDL wrapper
.
Select “Copy generated wrapper to allow user edits” and click
OK
.
The design_1_wrapper.vhd file can be found in the
./sources_1/imports/hdl/ folder.
The design_1_wrapper.vhd created shows how a component can be added
to the top level design file APZU_top.vhd. See the APZU_top.vhd to see how
the design_1_wrapper component and the port map is added to the top
level APZU_top.vhd file. This is how the IP block logic is connect the top
level of the design.
If necessary, edit the APZU_top.vhd for use with your updated
design_1_wrapper.vhd.
Select Run Synthesis, Implementation, and Generate Bitstream
Select OK
