SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
17
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www.acromag.com
Table 3.1 Configuration Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0 Device
ID
0x7731 APZU-301(E)
0x7733 APZU-303(E)
0x7734 APZU-304(E)
Vendor ID
16D5
1
Status Command
2
Class Code=118000
Rev ID=00
3
BIST Header Latency Cache
4:6
32-bit Memory Base Address for Memory Accesses to PCIe
1M Space
(BAR0)
32K Space
(BAR1)
64K Space
(BAR2)
7:10
Not Used
11 Subsystem
ID
0x7731 APZU-301(E)
0x7733 APZU-303(E)
0x7734 APZU-304(E)
Subsystem Vendor ID
16D5
12
Not Used
13,14
Reserved
15
Max_Lat Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 1M byte block of memory (BAR0), to access the
Zynq DMA registers. The PCIe bus decodes 1M bytes for BAR0 for this
memory space.
This board is allocated a 32K byte block of memory (BAR1), to access the
programmable logic registers. The PCIe bus decodes 32K bytes for BAR1 for
this memory space.
The memory space address map for the APZU+ is shown in Table 3.2. The
Zynq memory space allocated for the programmable logic starts at
0xA000_0000. An ingress translation register maps BAR1 PCIe bus 32K byte
space into the Zynq memory space starting at 0xA000_0000. Note that the
base address for the board (BAR1) in memory space must be added to
0xA000_0000 to properly access the FPGA programmable logic registers.
Register accesses as 32, 16, and 8-bit data in memory space are permitted.
In addition, the ingress translation register maps BAR2 PCIe bus space 64K
byte space into the Zynq DDR memory space starting at 0x100_0000.
