SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
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www.acromag.com
APZU-304
The data direction (input or output) of the 14 LVDS channels is selected via
bits-0 through 13 of this register.
The data direction control bit corresponds to the data bit location. For
example, data direction control bit-3 controls data bit-3. Setting a bit high
configures the corresponding channel data direction for output. Setting the
control bit low configures the corresponding channel data direction for
input.
The default power-up state of these registers is logic low. Thus, all channels
are configured as inputs on system reset or power-up. The unused upper
bits of this register are “Not Used” and will always read low (0’s). Reading
or writing to this register is possible via 32-bit, 16-bit or 8-bit data transfers.
Interrupt Enable Register (Read/Write) - (BAR1 + 0x0000 0010)
Interrupt Type (COS or H/L) Configuration Register (Read/Write) - (BAR1 + 0x0000 0014)
APZU-301 (28 Channels)
APZU-303 (20 Channels)
APZU-304 (14 Channels)
The Interrupt Type Configuration Registers determine the type of input
channel transition that will generate an interrupt for each of the possible
interrupting channels. A “0” bit selects interrupt on level. An interrupt will
be generated when the input channel level specified by the Interrupt
Polarity Register occurs (i.e. Low or High level transition interrupt). A “1” bit
means the interrupt will occur when a Change-Of-State (COS) occurs at the
corresponding input channel (i.e. any state transition, low to high or high to
low).
The Interrupt Type Configuration register at base a offset
0x0000_0014H is used to control all channel type configurations. For
example, channel 0 is controlled via data bit-0. All bits are set to “0”
following a reset which means that, if enabled, the inputs will cause
interrupts for the levels specified by the digital input channel Interrupt
Polarity Register.
Channel read or write operations use 8-bit, 16-bit, or 32-bit data transfers.
Note that interrupts will not occur unless they are enabled.
APZU-301 (28 Channels)
APZU-303 (20 Channels)
APZU-304 (14 Channels)
The digital input channel Interrupt Enable Registers provide a mask bit for
each of the possible interrupt channels. A “0” bit will prevent the
corresponding input channel from generating an external interrupt. A “1”
bit will allow the corresponding input channel to generate an interrupt.
Channel 0 is controlled via data bit-0 and channel 1 via data bit-1, etc.
All bits are set to “0” following a reset which means that all interrupts will
be disabled.
