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Chapter 4
NOTE:
BIOS does not support Memory Data Scrubber Error.
Memory Error Handling in non-RAS Mode
If memory RAS features are not enabled in BIOS Setup, BIOS will apply “10 SBE errors in one hour”
implementation. Enabling of this implementation and RAS features are mutually-exclusive and automatically
handled by system BIOS.
In non-RAS mode, BIOS maintains a counter for Single Bit ECC (SBE) errors. If ten SBE errors occur within an
hour, BIOS will disable SBE detection in the chipset to prevent the System Event Log (SEL) from being filled
up, and the OS from being halted.
In non-RAS mode, BIOS will assert a Non-Maskable-Interrupt (NMI) on the first Double Bit ECC (DBE) error.
Table 2. Memory Error Handling in non-RAS mode
DIMM Enabling
Setting the “Memory Retest” option to “Enabled” in BIOS Setup will bring all DIMM(s) back on line regardless
of current states.
After replacing faulty DIMM(s), the “Memory Retest” option must be set to “Enabled”.
Note:
this step is not required if faulty DIMM(s) were not taken off-line.
Single-bit ECC Error Throttling Prevention
The system detects, corrects, and logs correctable errors. As long as these errors occur infrequently, the
system should continue to operate without a problem.
Occasionally, correctable errors are caused by a persistent failure of a single component. For example, a
broken data line on a DIMM would exhibit repeated errors until replaced. Although these errors are
correctable, continual calls to the error logger can throttle the system, preventing any further useful work.
For this reason, the system counts certain types of correctable errors and disables reporting if they occur too
frequently. Correction remains enabled but calls to the error handler are disabled. This allows the system to
continue running, despite a persistent correctable failure. The BIOS adds an entry to the event log to indicate
Memory with RAS mode
SE7320VP2
Sparing mode /
Mirroring mode
When Sparing or Mirroring occurs:
- BIOS will not report memory RAS
configuration to mBMC.
- BIOS will light the faulty DIMM LED.
DIMMs which go off line during OS runtime will
be back online on the next system reboot
without user intervention.
Sparing and Mirroring states are not sticky
across system reset.
Non-RAS mode
SE7320VP2
Single Bit ECC (SBE)
errors
SBE error events will not be logged.
On the 10th SBE error, BIOS will:
- Disable SBE detection in chipset.
- Light the faulty DIMM LED.
Double Bit ECC (DBE)
errors
On the 1st DBE error, BIOS will:
- Log DBE record to SEL.
- Light the faulty DIMM LED.
- Generate NMI.
Содержание Altos R510
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