Abov MC97F2664, Руководство пользователя

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MC97F2664
142 April 11, 2014 Ver. 1.4
11.6.6.1 Timer/Counter 4/5 Register Description
The timer/counter 4/5 register consists of timer 4/5 A data high register (TnADRH), timer 4/5 A data low register
(TnADRL), timer 4/5 B data high register (TnBDRH), timer 4/5 B data low register (TnBDRL), timer 4/5 control
high register (TnCRH) and timer 4/5 control low register (TnCRL).
11.6.6.2 Register Description for Timer/Counter 4/5
TnADRH (Timer n A data High Register) : CDH/D5H, n= 4 and 5
7 6 5 4 3 2 1 0
TnADRH7 TnADRH6 TnADRH5 TnADRH4 TnADRH3 TnADRH2 TnADRH1 TnADRH0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
TnADRH[7:0] Tn A Data High Byte
TnADRL (Timer n A Data Low Register) : CCH/D4H, n= 4 and 5
7 6 5 4 3 2 1 0
TnADRL7 TnADRL6 TnADRL5 TnADRL4 TnADRL3 TnADRL2 TnADRL1 TnADRL0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
TnADRL[7:0] Tn A Data Low Byte
NOTE) Do not write
“0000H” in the TnADRH/TnADRL register when
PPG mode
TnBDRH (Timer n B Data High Register) : CFH/D7H, n= 4 and 5
7 6 5 4 3 2 1 0
TnBDRH7 TnBDRH6 TnBDRH5 TnBDRH4 TnBDRH3 TnBDRH2 TnBDRH1 TnBDRH0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
TnBDRH[7:0] Tn B Data High Byte
TnBDRL (Timer n B Data Low Register) : CEH/D6H, n= 4 and 5
7 6 5 4 3 2 1 0
TnBDRL7 TnBDRL6 TnBDRL5 TnBDRL4 TnBDRL3 TnBDRL2 TnBDRL1 TnBDRL0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
TnBDRL[7:0] Tn B Data Low Byte