Abov MC97F2664, Руководство пользователя

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MC97F2664
April 11, 2014 Ver. 1.4 39
7.11 UART Characteristics
Table 7-11 UART Characteristics
(T
A
= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, f
XIN
=11.1MHz)
Parameter Symbol MIN TYP MAX Unit
Serial port clock cycle time t
SCK
1250 t
CPU
x 16 1650 ns
Output data setup to clock rising edge t
S1
590 t
CPU
x 13
–
ns
Clock rising edge to input data valid t
S2
– –
590 ns
Output data hold after clock rising edge t
H1
t
CPU
- 50 t
CPU
–
ns
Input data hold after clock rising edge t
H2
0
– –
ns
Serial port clock High, Low level width t
HIGH
, t
LOW
470 t
CPU
x 8 970 ns
t
HIGH
t
LOW
t
SCK
Figure 7.5 Waveform for UART Timing Characteristics
Shift Clock
Data Out D1 D2 D3 D4 D5 D6 D7 D0
Valid Data In Valid Valid Valid Valid Valid Valid Valid
t
SCK
t
S1
t
H1
t
H2
t
S2
Figure 7.6 Timing Waveform for the UART Module