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MC97F2664

192

April 11, 2014 Ver. 1.4

Figure 11.48 USI0/1 SPI Clock Formats when CPHAn=1 (where n = 0 and 1)

When CPHAn=1, the slave begins to drive its MISOn output when SSn goes active low, but the data is not

defined until the first SCKn edge. The first SCKn edge shifts the first bit of data from the shifter onto the MOSIn

output of the master and the MISOn output of the slave. The next SCKn edge causes both the master and slave

to sample the data bit value on their MISOn and MOSIn inputs, respectively. At the third SCKn edge, the USI0/1

shifts the second data bit value out to the MOSIn and MISOn output of the master and slave respectively. When

CPHAn

=1, the slave’s SSn input is not required to go to its inactive high level between transfers.

Because the SPI logic reuses the USI0/1 resources, SPI mode of operation is similar to that of synchronous or

asynchronous operation. An SPI transfer is initiated by checking for the USI0/1 Data Register Empty flag

(DREn=1) and then writing a byte of data to the USInDR Register. In master mode of operation, even if

transmission is not enabled (TXEn=0), writing data to the USInDR register is necessary because the clock SCKn

is generated from transmitter block.

SCKn

(CPOLn=1)

MISOn

MOSIn

SCKn

(CPOLn=0)

/SSn OUT
(MASTER)

BIT7
BIT0

/SSn IN

(SLAVE)

BIT6
BIT1

…
…

BIT2
BIT5

BIT0
BIT7

BIT1
BIT6

SAMPLE

MSB First

LSB First

Содержание MC97F2664

Страница 1: ...MC97F2664 April 11 2014 Ver 1 4 1 ABOV SEMICONDUCTOR Co Ltd 8 BIT MICROCONTROLLERS MC97F2664 User s Manual Ver 1 4...

Страница 2: ...Layout Add Figure 7 18 Recommended Circuit and Layout with SMPS Power VERSION 1 2 January 11 2013 Add 0 1uF Bypass capacitor in Internal RC Oscillator characteristics Change 14 24mA 10 18mA to LVR LV...

Страница 3: ...tor Characteristics 34 7 8 DC Characteristics 35 7 9 AC Characteristics 37 7 10 SPI Characteristics 38 7 11 UART Characteristics 39 7 12 I2C Characteristics 40 7 13 Data Retention Voltage in Stop Mode...

Страница 4: ...11 4 Watch Timer 121 11 5 Timer 0 1 2 3 124 11 6 Timer 4 5 135 11 7 Timer 6 7 8 9 145 11 8 Buzzer Driver 156 11 9 SPI 2 3 159 11 10 UART2 3 4 165 11 11 USI0 1 UART SPI I2C 179 11 12 Baud Rate setting...

Страница 5: ...cteristics 39 Figure 7 6 Timing Waveform for the UART Module 39 Figure 7 7 I2C Timing 40 Figure 7 8 Stop Mode Release Timing when Initiated by an Interrupt 41 Figure 7 9 Stop Mode Release Timing when...

Страница 6: ...nd 5 138 Figure 11 18 Express Timer Overflow in Capture Mode where n 4 and 5 138 Figure 11 19 16 Bit PPG Mode for Timer 4 5 where n 4 and 5 139 Figure 11 20 16 Bit PPG Mode Timming chart for Timer 4 5...

Страница 7: ...05 Figure 11 60 USI0 1 I2C Block Diagram where n 0 and 1 206 Figure 11 61 12 bit ADC Block Diagram 218 Figure 11 62 A D Analog Input Pin with Capacitor 218 Figure 11 63 A D Power AVREF Pin with Capaci...

Страница 8: ...Table 7 19 Sub Oscillation Stabilization Characteristics 45 Table 8 1 SFR Map Summary 57 Table 8 2 Extended SFR Map Summary 58 Table 8 3 SFR Map 59 Table 8 4 Extended SFR Map 63 Table 9 1 Port Regist...

Страница 9: ...SI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies 216 Table 11 21 ADC Register Map 220 Table 12 1 Peripheral Operation during Power Down Mode 224 Table 12 2 Power Down Operation Regis...

Страница 10: ...of FLASH 256 bytes of IRAM 4 096 bytes of XRAM general purpose I O basic interval timer watchdog timer 8 16 bit timer counter 16 bit PPG output 8 bit PWM output watch timer buzzer driving port SPI UA...

Страница 11: ...4V Low Voltage Reset 14 level detect 1 60V 2 00V 2 10V 2 20V 2 32V 2 44V 2 59V 2 75V 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V Low Voltage Indicator 13 level detect 2 00V 2 10V 2 20V 2 32V 2 44V 2 59V 2 75...

Страница 12: ...ering Information Table 1 1 Ordering Information of MC97F2664 Device name ROM size IRAM size XRAM size Package MC97F2664L 64k bytes FLASH 256 bytes 4 096 bytes 64 LQFP 1010 MC97F2664L14 64 LQFP 1414 M...

Страница 13: ...system The OCD2 can read or change the value of MCU internal memory and I O peripherals And the OCD2 also controls MCU internal debugging logic it means OCD2 controls emulation step run monitoring et...

Страница 14: ...emulator It can write code in MCU device too because OCD debugging supports ISP In System Programming It does not require additional H W except developer s target system Gang programmer It programs 8...

Страница 15: ...PWM3O P53 EINT13 P53 EC3 P57 16 Bit Timer 4 T4O PWM4O P30 EINT14 P30 EC4 P72 16 Bit Timer 5 T5O PWM5O P31 EINT15 P31 EC5 P73 UART2 TXD2 P44 RXD2 P45 P2 Port P20 EINT17 T7O PWM7O P21 EINT18 T8O PWM8O...

Страница 16: ...6 T6O PWM6O P33 BUZO EC6 P34 MOSI2 P35 MISO2 EC7 P36 SCK2 EC8 P37 SS2 EC9 P20 EINT17 T7O PWM7O P30 EINT14 T4O PWM4O P31 EINT15 T5O PWM5O P73 SS3 EC5 P74 EC6 P23 TXD4 P21 EINT18 T8O PWM8O P22 EINT19 T9...

Страница 17: ...M6O P33 BUZO EC6 P34 MOSI2 P35 MISO2 EC7 P36 SCK2 EC8 P37 SS2 EC9 P20 EINT17 T7O PWM7O P30 EINT14 T4O PWM4O P31 EINT15 T5O PWM5O P73 SS3 EC5 P74 EC6 P23 TXD4 P21 EINT18 T8O PWM8O P22 EINT19 T9O PWM9O...

Страница 18: ...6O P33 BUZO EC6 P34 MOSI2 P35 MISO2 EC7 P36 SCK2 EC8 P37 SS2 EC9 P20 EINT17 T7O PWM7O P30 EINT14 T4O PWM4O P31 EINT15 T5O PWM5O P73 SS3 EC5 P74 EC6 P23 TXD4 P21 EINT18 T8O PWM8O P22 EINT19 T9O PWM9O P...

Страница 19: ...ISO1 P47 RXD3 P46 TXD3 P32 EINT16 T6O PWM6O P33 BUZO EC6 P34 MOSI2 P35 MISO2 EC7 P36 SCK2 EC8 P37 SS2 EC9 P20 EINT17 T7O PWM7O P30 EINT14 T4O PWM4O P31 EINT15 T5O PWM5O P21 EINT18 T8O PWM8O P22 EINT19...

Страница 20: ...MC97F2664 20 April 11 2014 Ver 1 4 4 Package Diagram Figure 4 1 64 Pin LQFP 1010 Package...

Страница 21: ...MC97F2664 April 11 2014 Ver 1 4 21 Figure 4 2 64 Pin LQFP 1414 Package...

Страница 22: ...MC97F2664 22 April 11 2014 Ver 1 4 Figure 4 3 64 Pin QFN Package...

Страница 23: ...MC97F2664 April 11 2014 Ver 1 4 23 Figure 4 4 44 Pin MQFP 1010 Package...

Страница 24: ...O Port 2 is a bit programmable I O port which can be configured as a schmitt trigger input a push pull output or an open drain output A pull up resistor can be specified in 1 bit unit The P23 P27 are...

Страница 25: ...rain output A pull up resistor can be specified in 1 bit unit Input SS0 P61 SCK0 P62 RXD0 SCL0 MISO0 DSCL P63 TXD0 SDA0 MOSI0 DSDA P64 XOUT P65 XIN P66 SXIN P67 SXOUT P70 I O Port 7 is a bit programma...

Страница 26: ...O T8O I O Timer 8 interval output Input P21 EINT8 PWM8O T9O I O Timer 9 interval output Input P22 EINT9 PWM9O PWM0O I O Timer 0 pulse output Input P50 EINT0 T0O PWM1O I O Timer 1 pulse output Input P5...

Страница 27: ...P37 EC9 SS3 I O SPI 3 slave select input Input P73 EC5 TXD0 I O UART 0 data output Input P63 SDA0 MOSI0 DSDA TXD1 I O UART 1 data output Input P40 SDA1 MOSI1 TXD2 I O UART 2 data output Input P44 TXD3...

Страница 28: ...RUNFLAG I O On chip debugger run flag NOTE3 with a pull down resistor Input XIN I O Main oscillator pins Input P65 XOUT P64 SXIN I O Sub oscillator pins Input P66 SXOUT P67 VDD VSS Power input pins N...

Страница 29: ...OPEN DRAIN REGISTER DATA REGISTER DIRECTION REGISTER MUX 0 1 MUX 1 0 CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or SUB FUNC DATA INPUT SUB FUNC DIRECTION SUB FUNC ENAB...

Страница 30: ...0 INTERRUPT ENABLE EXTERNAL INTERRUPT Q D CP r VDD FLAG CLEAR POLARITY REG MUX 1 0 DEBOUNCE ENABLE Q D CP r DEBOUNCE CLK CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or S...

Страница 31: ...beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at any other conditions beyond those ind...

Страница 32: ...ersion Time tCON 12bit resolution 8MHz 20 s Analog Input Voltage VAN VSS AVREF V Analog Reference Voltage AVREF Note 3 1 8 VDD VDD18 1 8 V Analog Input Leakage Current IAN AVREF 5 12V 2 A ADC Operatin...

Страница 33: ...haracteristics TA 40 C 85 C VDD 1 8V 5 5V VSS 0V Parameter Symbol Conditions MIN TYP MAX Unit Detection Level VLVR VLVI The LVR can select all levels but LVI can select other levels except 1 60V 1 60...

Страница 34: ...40 C to 85 C 3 5 Clock Duty Ratio TOD 40 50 60 Stabilization Time THFS 100 s IRC Current IIRC Enable 0 2 mA Disable 0 1 A NOTE A 0 1uF bypass capacitor should be connected to VDD and VSS Refer to the...

Страница 35: ...5V IOH 2mA All output ports VDD 1 0 V Output Low Voltage VOL1 VDD 4 5V IOL 5mA All output ports except VOL2 1 0 V VOL2 VDD 4 5V IOL 15mA P2 P3 P50 53 1 0 V Input High Leakage Current IIH All input por...

Страница 36: ...10 1 0 2 0 fIRC 16MHz VDD 5V 10 1 2 2 4 IDD3 fXIN 32 768kHz VDD 3V 10 TA 25 C Sub RUN 60 0 90 0 A IDD4 Sub IDLE 8 0 16 0 A IDD5 STOP VDD 5V 10 TA 25 C 0 5 3 0 A NOTES 1 Where the fXIN is an external m...

Страница 37: ...t input high low width tIWH tIWL All interrupt VDD 5V 200 ns External Counter Input High Low Pulse Width tECWH tECWL ECn VDD 5 V n 0 9 200 External Counter Transition Time tREC tFEC ECn VDD 5 V n 0 9...

Страница 38: ...ce 200 Output Clock High Low Pulse Width tSCKH tSCKL Internal SCK source 70 Input Clock High Low Pulse Width External SCK source 70 First Output Clock Delay Time tFOD Internal External SCK source 100...

Страница 39: ...x 13 ns Clock rising edge to input data valid tS2 590 ns Output data hold after clock rising edge tH1 tCPU 50 tCPU ns Input data hold after clock rising edge tH2 0 ns Serial port clock High Low level...

Страница 40: ...h tSCLH 4 0 0 6 s Clock Low Pulse Width tSCLL 4 7 1 3 Bus Free Time tBF 4 7 1 3 Start Condition Setup Time tSTSU 4 7 0 6 Start Condition Hold Time tSTHD 4 0 0 6 Stop Condition Setup Time tSPSU 4 0 0 6...

Страница 41: ...ive VDD NOTE tWAIT is the same as the selected bit overflow of BIT X 1 BIT Clock INT Request Execution of STOP Instruction Data Retention Stop Mode Normal Operating Mode VIH tWAIT VDDDR Figure 7 8 Sto...

Страница 42: ...FBR 5 s Flash Programming Frequency fPGM 0 4 MHz Endurance of Write Erase Sector 0 1019 NFWE 10 000 Times Endurance of Write Erase Sector 1020 1023 100 000 NOTE During a flash operation SCLK 1 0 of SC...

Страница 43: ...l Main oscillation frequency 1 8V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 12 0 3 0V 5 5V 0 4 16 0 Ceramic Oscillator Main oscillation frequency 1 8V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 12 0 3 0V 5 5V 0 4 16 0 Exter...

Страница 44: ...haracteristics TA 40 C 85 C VDD 1 8V 5 5V Oscillator Parameter Condition MIN TYP MAX Unit Crystal Sub oscillation frequency 1 8V 5 5V 32 32 768 38 kHz External Clock SXIN input frequency 32 100 kHz SX...

Страница 45: ...voltage range 60 ms Ceramic 10 ms External Clock fXIN 0 4 to 16MHz XIN input high and low width tXH tXL 31 1250 ns tXH tXL XIN 0 2VDD 0 8VDD 1 fXIN Figure 7 14 Clock Timing Measurement at XIN 7 19 Sub...

Страница 46: ...il 11 2014 Ver 1 4 7 20 Operating Voltage Range 1 8 0 4MHz 3 0 5 5 16 0MHz fXIN 0 4 to 16MHz Supply voltage V 4 2MHz 1 8 5 5 32 768KHz Supply voltage V fSUB 32 to 38KHz 12 0MHz 2 7 Figure 7 16 Operati...

Страница 47: ...y for noise immunity X tal SXOUT SXIN 32 768kHz The main and sub crystal should be within 1cm from the pins of MCU on the PCB layout 0 1uF VDD VCC The MCU power line VDD and VSS should be separated fr...

Страница 48: ...ommended C2 47uF 25V more The R1 and C2 should be as close by the C3 as possible 3 The C3 capacitor is used for temperature compensation because an electrolytic capacitor becomes worse characteristics...

Страница 49: ...a presented in this section is a statistical summary of data collected on units from different lots over a period of time Typical represents the mean of the distribution while max or min represents me...

Страница 50: ...Figure 7 21 SUB RUN IDD3 Current Figure 7 22 SUB IDLE IDD4 Current 0 0 20 0 40 0 60 0 80 0 100 0 120 0 2 5V 3 0V 3 5V 4 0V 4 5V 5 0V 5 5V uA 40 25 85 0 0 5 0 10 0 15 0 20 0 25 0 30 0 35 0 2 5V 3 0V 3...

Страница 51: ...MC97F2664 April 11 2014 Ver 1 4 51 Figure 7 23 STOP IDD5 Current 0 00 1 00 2 00 3 00 4 00 5 00 2 5V 3 0V 3 5V 4 0V 4 5V 5 0V 5 5V uA 40 25 85...

Страница 52: ...f addressing up to 64k bytes this device has just 64k bytes program memory space Figure 8 1 shows the map of the lower part of the program memory After reset the CPU begins execution from location 000...

Страница 53: ...MC97F2664 April 11 2014 Ver 1 4 53 FFFFH 0000H 64K Bytes Figure 8 1 Program Memory 64k Bytes Including Interrupt Vector Region...

Страница 54: ...er 128 bytes and SFR space occupying the same block of addresses 80H through FFH although they are physically separate entities The lower 128 bytes of RAM are present in all 8051 devices as mapped in...

Страница 55: ...tes 07H 00H 8 Bytes R7 R6 R5 R4 R3 R2 R1 R0 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C...

Страница 56: ...ytes XRAM This area has no relation with RAM FLASH It can be read and written to through SFR with 8 bit unit External RAM 4096 Bytes Indirect Addressing 0000H 0FFFH Extended Special Function Registers...

Страница 57: ...P6IO T5CRL T5CRH T5ADRL T5ADRH T5BDRL T5BDRH 0C8H OSCCR P5IO T4CRL T4CRH T4ADRL T4ADRH T4BDRL T4BDRH 0C0H P7 P4IO SPI2CR SPI2DR SPI2SR SPI3CR SPI3DR SPI3SR 0B8H P6 P3IO T2CR T2CNT T2DR T2CDR T3CR T3C...

Страница 58: ...4DR 1040H UART3CR1 UART3CR2 UART3CR3 UART3ST UART3BD UART3DR 1038H UART2CR1 UART2CR2 UART2CR3 UART2ST UART2BD UART2DR 1030H USI1ST1 USI1ST2 USI1BD USI1SDHR USI1DR USI1SCLR USI1SCHR USI1SAR 1028H USI1C...

Страница 59: ...8EH Watch Dog Timer Data Register WDTDR W 1 1 1 1 1 1 1 1 Watch Dog Timer Counter Register WDTCNT R 0 0 0 0 0 0 0 0 8FH Watch Timer Control Register WTCR R W 0 0 0 0 0 0 0 90H P2 Data Register P2 R W...

Страница 60: ...1L R W 0 0 0 0 0 0 0 0 ADH External Interrupt Polarity 1 High Register EIPOL1H R W 0 0 0 0 0 0 0 0 AEH External Interrupt Polarity 2 Low Register EIPOL2L R W 0 0 0 0 0 0 AFH External Interrupt Polarit...

Страница 61: ...r 4 A Data Low Register T4ADRL R W 1 1 1 1 1 1 1 1 CDH Timer 4 A Data High Register T4ADRH R W 1 1 1 1 1 1 1 1 CEH Timer 4 B Data Low Register T4BDRL R W 1 1 1 1 1 1 1 1 CFH Timer 4 B Data High Regist...

Страница 62: ...1 1 1 EDH Timer 8 A Data High Register T8ADRH R W 1 1 1 1 1 1 1 1 EEH Timer 8 B Data Low Register T8BDRL R W 1 1 1 1 1 1 1 1 EFH Timer 8 B Data High Register T8BDRH R W 1 1 1 1 1 1 1 1 F0H B Register...

Страница 63: ...ister P3PU R W 0 0 0 0 0 0 0 0 100CH P4 Pull up Resistor Selection Register P4PU R W 0 0 0 0 0 0 0 0 100DH P5 Pull up Resistor Selection Register P5PU R W 0 0 0 0 0 0 0 0 100EH P6 Pull up Resistor Sel...

Страница 64: ...0 102BH USI1 Control Register 4 USI1CR4 R W 0 0 0 0 0 0 0 102CH Reserved 102DH Reserved 102EH Reserved 102FH Reserved 1030H USI1 Status Register 1 USI1ST1 R W 1 0 0 0 0 0 0 0 1031H USI1 Status Registe...

Страница 65: ...gister UART4ST R W 1 0 0 0 0 0 0 0 104CH UART4 Baud Rate Generation Register UART4BD R W 1 1 1 1 1 1 1 1 104DH UART4 Data Register UART4DR R W 0 0 0 0 0 0 0 0 104EH Reserved 104FH Reserved 1050H A D C...

Страница 66: ...Initial value 07H SP Stack Pointer XSP Extend Stack Pointer 91H 7 6 5 4 3 2 1 0 XSP R W R W R W R W R W R W R W R W Initial value 00H XSP Extended Stack Pointer The XSP is a high of stack pointer whe...

Страница 67: ...00H DPL1 Data Pointer Low 1 DPH1 Data Pointer Register High 1 85H 7 6 5 4 3 2 1 0 DPH1 R W R W R W R W R W R W R W R W Initial value 00H DPH1 Data Pointer High 1 PSW Program Status Word Register D0H...

Страница 68: ...inter Watch Register Low Byte F4H 7 6 5 4 3 2 1 0 SPWRL R W R W R W R W R W R W R W R W Initial value FFH SPWRL Stack Pointer Watch Low SPWRH Stack Pointer Watch Register High Byte F5H 7 6 5 4 3 2 1 0...

Страница 69: ...he stack pointer watch low register SWARL If the values are same SP 7 0 SWARL 7 0 the SPOVIFR bit is set to 1b At this time the XSP and SWARH registers are don t care 2 When the XSPEN bit of the XSPCR...

Страница 70: ...its are set by a system reset 9 2 3 Pull up Resistor Selection Register PxPU The on chip pull up resistor can be connected to I O ports individually with a pull up resistor selection register PxPU The...

Страница 71: ...ection Register P2PU 100AH XSFR R W 00H P2 Pull up Resistor Selection Register P2DB E9H R W 00H P2 Debounce Enable Register P2FSR 1012H XSFR R W 00H P2 Function Selection Register P3 98H R W 00H P3 Da...

Страница 72: ...0H P6 Open drain Selection Register P6PU 100EH XSFR R W 00H P6 Pull up Resistor Selection Register P6FSR 1016H XSFR R W 00H P6 Function Selection Register P7 C0H R W 00H P7 Data Register P7IO D9H R W...

Страница 73: ...0H P0 7 0 I O Data P0IO P0 Direction Register 99H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R W R W R W R W R W R W R W R W Initial value 00H P0IO 7 0 P0 Data I O Direction 0 Inp...

Страница 74: ...Function select 0 I O Port 1 AN14 Function P0FSR6 P06 Function select 0 I O Port 1 AN13 Function P0FSR5 P05 Function select 0 I O Port 1 AN12 Function P0FSR4 P04 Function select 0 I O Port 1 AN11 Func...

Страница 75: ...0 I O Data P1IO P1 Direction Register A1H 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R W R W R W R W R W R W R W R W Initial value 00H P1IO 7 0 P1 Data I O Direction 0 Input 1 Out...

Страница 76: ...nce of P13 Port 0 Disable 1 Enable P12DB Configure Debounce of P12 Port 0 Disable 1 Enable P11DB Configure Debounce of P11 Port 0 Disable 1 Enable P10DB Configure Debounce of P10 Port 0 Disable 1 Enab...

Страница 77: ...le when input 1 AN6 Function P1FSR5 P15 Function select 0 I O Port EINT5 function possible when input 1 AN5 Function P1FSR4 P14 Function select 0 I O Port EINT4 function possible when input 1 AN4 Func...

Страница 78: ...P2 Direction Register B1H 7 6 5 4 3 2 1 0 P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO R W R W R W R W R W R W R W R W Initial value 00H P2IO 7 0 P2 Data I O Direction 0 Input 1 Output NOTE EINT8 E...

Страница 79: ...rt 0 Disable 1 Enable P25DB Configure Debounce of P25 Port 0 Disable 1 Enable P22DB Configure Debounce of P22 Port 0 Disable 1 Enable P21DB Configure Debounce of P21 Port 0 Disable 1 Enable P20DB Conf...

Страница 80: ...al value 00H P2FSR3 P23 Function select 0 I O Port 1 TXD4 Function P2FSR2 P22 Function select 0 I O Port EINT19 function possible when input 1 T9O PWM9O Function P2FSR1 P21 Function select 0 I O Port...

Страница 81: ...3IO P3 Direction Register B9H 7 6 5 4 3 2 1 0 P37IO P36IO P35IO P34IO P33IO P32IO P31IO P30IO R W R W R W R W R W R W R W R W Initial value 00H P3IO 7 0 P3 Data I O Direction 0 Input 1 Output NOTE EIN...

Страница 82: ...DB Configure Debounce of P32 Port 0 Disable 1 Enable P31DB Configure Debounce of P31 Port 0 Disable 1 Enable P30DB Configure Debounce of P30 Port 0 Disable 1 Enable NOTES 1 If a level is not detected...

Страница 83: ...tion select 0 I O Port EC7 function possible when input 1 MISO2 Function P3FSR5 P34 Function select 0 I O Port 1 MOSI2 Function P3FSR 4 3 P33 Function select P3FSR4 P3FSR3 description 0 0 I O Port 0 1...

Страница 84: ...Data P4IO P4 Direction Register C1H 7 6 5 4 3 2 1 0 P47IO P46IO P45IO P44IO P43IO P42IO P41IO P40IO R W R W R W R W R W R W R W R W Initial value 00H P4IO 7 0 P4 Data I O Direction 0 Input 1 Output NO...

Страница 85: ...SR0 R W R W R W R W R W Initial value 00H P4FSR4 P46 Function select 0 I O Port 1 TXD3 Function P4FSR3 P44 Function Select 0 I O Port 1 TXD2 Function P4FSR2 P42 Function select 0 I O Port 1 SCK1 Funct...

Страница 86: ...irection Register C9H 7 6 5 4 3 2 1 0 P57IO P56IO P55IO P54IO P53IO P52IO P51IO P50IO R W R W R W R W R W R W R W R W Initial value 00H P5IO 7 0 P5 Data I O Direction 0 Input 1 Output NOTE EINT10 EINT...

Страница 87: ...t EINT13 function possible when input 1 T3O PWM3O Function P5FSR2 P52 Function select 0 I O Port EINT12 function possible when input 1 T2O PWM2O Function P5FSR1 P51 Function Select 0 I O Port EINT11 f...

Страница 88: ...P6IO P6 Direction Register D1H 7 6 5 4 3 2 1 0 P67IO P66IO P65IO P64IO P63IO P62IO P61IO P60IO R W R W R W R W R W R W R W R W Initial value 00H P6IO 7 0 P6 Data I O Direction 0 Input 1 Output NOTE SS...

Страница 89: ...6FSR6 P67 Function select 0 I O Port 1 SXOUT Function P6FSR5 P66 Function select 0 I O Port 1 SXIN Function P6FSR4 P65 Function select 0 I O Port 1 XIN Function P6FSR3 P64 Function Select 0 I O Port 1...

Страница 90: ...O P7 Direction Register D9H 7 6 5 4 3 2 1 0 P77IO P76IO P75IO P74IO P73IO P72IO P71IO P70IO R W R W R W R W R W R W R W R W Initial value 00H P7IO 7 0 P7 Data I O Direction 0 Input 1 Output NOTE EC4 E...

Страница 91: ...R3 P7FSR2 P7FSR1 P7FSR0 R W R W R W R W Initial value 00H P7FSR3 P73 Function Select 0 I O Port 1 EC6 Function P7FSR2 P72 Function select 0 I O Port EC4 function possible when input 1 SCK3 Function P7...

Страница 92: ...abled through four pair of interrupt enable registers IE IE1 IE2 IE3 Each bit of IE IE1 IE2 IE3 register individually enables disables the corresponding interrupt source Overall control is provided by...

Страница 93: ...external interrupt flag 1 register EIFLAG1 and external interrupt flag 2 register EIFLAG2 provides the status of external interrupts EINT11 Pin EINT13 Pin EINT15 Pin EINT17 Pin EINT10 Pin FLAG10 FLAG1...

Страница 94: ...FR 12 13 14 15 16 17 IE2 12 13 14 15 16 17 12 13 14 15 16 17 12 13 14 15 16 17 IE3 Timer 3 T3IFR Timer 2 OVF Timer 3 OVF T4OVIFR T3OVIFR EINT11 EIFLAG1 0 EINT13 EINT15 EINT17 EINT10 EINT12 EINT14 EINT...

Страница 95: ...INT9 IE1 3 10 Maskable 004BH SPI3 Interrupt INT10 IE1 4 11 Maskable 0053H External Interrupt 10 17 INT11 IE1 5 12 Maskable 005BH UART4 Rx Interrupt INT12 IE2 0 13 Maskable 0063H T6 7 8 9 Match Interr...

Страница 96: ...uction it needs 3 9 machine cycles to go to the interrupt service routine The interrupt service task is terminated by the interrupt return instruction RETI Once an interrupt request is generated the f...

Страница 97: ...f Interrupt Enable Register Case b Interrupt flag Register Figure 10 5 Effective Timing of Interrupt Flag Register Interrupt Flag Register Command Next Instruction Next Instruction After executing nex...

Страница 98: ...INT1 is occurred Then INT0 is served immediately and then the remain part of INT1 service routine is executed If the priority level of INT0 is same or lower than INT1 INT0 will be served after the INT...

Страница 99: ...9 Saving Restore Process Diagram and Sample Source Main Task Saving Register Restoring Register Interrupt Service Task INTxx PUSH PSW PUSH DPL PUSH DPH PUSH B PUSH ACC Interrupt_Processing POP ACC POP...

Страница 100: ...E IE1 IE2 IE3 Interrupt enable register consists of global interrupt control bit EA and peripheral interrupt control bits Total 24 peripherals are able to control interrupt 10 12 2 Interrupt Priority...

Страница 101: ...satisfied The flag is cleared when the interrupt service routine is executed Alternatively the flag can be cleared by writing 0 to it 10 12 4 External Interrupt Polarity Register EIPOL0H L EIPOL1H L E...

Страница 102: ...Interrupt Polarity 0 High Register EIFLAG1 A4H R W 00H External Interrupt Flag 1 Register EIPOL1L ACH R W 00H External Interrupt Polarity 1 Low Register EIPOL1H ADH R W 00H External Interrupt Polarity...

Страница 103: ...errupt bits 0 All Interrupt disable 1 All Interrupt enable INT5E Enable or Disable External Interrupt 0 7 EINT0 EINT7 0 Disable 1 Enable INT4E Enable or Disable SPI2 Interrupt 0 Disable 1 Enable INT3E...

Страница 104: ...or Disable External interrupt 10 17 EINT10 EINT17 0 Disable 1 Enable INT10E Enable or Disable SPI3 interrupt 0 Disable 1 Enable INT9E Enable or Disable UART3 Tx interrupt 0 Disable 1 Enable INT8E Enab...

Страница 105: ...3 match interrupt 0 Disable 1 Enable INT16E Enable or Disable External interrupt 8 A 18 19 EINT8 EINTA EINT18 EINT19 0 Disable 1 Enable INT15E Enable or Disable Timer 4 match interrupt 0 Disable 1 Ena...

Страница 106: ...Enable or Disable Timer 0 1 2 3 overflow interrupt 0 Disable 1 Enable INT22E Enable or Disable BIT Interrupt 0 Disable 1 Enable INT21E Enable or Disable WDT Interrupt 0 Disable 1 Enable INT20E Enable...

Страница 107: ...0 Select IE Interrupt Priority IP0Hx IP0Lx Description 0 0 level 0 lowest 0 1 level 1 1 0 level 2 1 1 level 3 highest IP1L Interrupt Priority 1 Low Register 9AH 7 6 5 4 3 2 1 0 IP1L5 IP1L4 IP1L3 IP1L2...

Страница 108: ...Select IE2 Interrupt Priority IP2Hx IP2Lx Description 0 0 level 0 lowest 0 1 level 1 1 0 level 2 1 1 level 3 highest IP3L Interrupt Priority 3 Low Register 9EH 7 6 5 4 3 2 1 0 IP3L5 IP3L4 IP3L3 IP3L2...

Страница 109: ...1 0 POL7 POL6 POL5 POL4 R W R W R W R W R W R W R W R W Initial value 00H EIPOL0H 7 0 External interrupt EINT7 EINT6 EINT5 EINT4 polarity selection POLn 1 0 Description 0 0 No interrupt at any edge 0...

Страница 110: ...POL17 POL16 POL15 POL14 R W R W R W R W R W R W R W R W Initial value 00H EIPOL1H 7 0 External interrupt EINT14 EINT15 EINT16 EINT17 polarity selection POLn 1 0 Description 0 0 No interrupt at any edg...

Страница 111: ...FH 7 6 5 4 3 2 1 0 POL19 POL18 R W R W R W R W Initial value 00H EIPOL2H 3 0 External interrupt EINT18 EINT19 polarity selection POLn 1 0 Description 0 0 No interrupt at any edge 0 1 Interrupt on risi...

Страница 112: ...or and the default division rate is sixteen In order to stabilize system internally it is used 1MHz INT RC oscillator on POR Calibrated Internal RC Oscillator 16 MHz INT RC OSC 1 16 MHz INT RC OSC 2 8...

Страница 113: ...r register uses clock control for system operation The clock generation consists of System and clock control register and oscillator control register 11 1 5 Register Description for Clock Generator SC...

Страница 114: ...1 INT RC 16 1MHz 0 1 0 INT RC 8 2MHz 0 1 1 INT RC 4 4MHz 1 0 0 INT RC 2 8MHz 1 0 1 INT RC 1 16MHz Other values Not used IRCE Control the Operation of the Internal RC Oscillator 0 Enable operation of I...

Страница 115: ...It also provides a basic interval timer interrupt BITIFR The MC97F2664 has these basic interval timer BIT features During Power On BIT gives a stable clock generation time On exiting Stop mode BIT giv...

Страница 116: ...The basic interval timer register consists of basic interval timer counter register BITCNT and basic interval timer control register BITCR If BCLR bit is set to 1 BITCNT becomes 0 and then counts up A...

Страница 117: ...BIT interrupt generation BITCK 1 0 Select BIT clock source BITCK1 BITCK0 Description 0 0 fx 4096 0 1 fx 1024 1 0 fx 128 1 1 fx 16 BCLR If this bit is written to 1 BIT Counter is cleared to 0 0 Free R...

Страница 118: ...up After 1 machine cycle this bit is cleared to 0 automatically The watchdog timer consists of 8 bit binary counter and the watchdog timer data register When the value of 8 bit binary counter is equal...

Страница 119: ...p Table 11 3 Watch Dog Timer Register Map Name Address Dir Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8DH R W 00H Watch D...

Страница 120: ...ue 1 NOTE Do not write 0 in the WDTDR register WDTCR Watch Dog Timer Control Register 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL WDTCK WDTIFR R W R W R W R W R W Initial value 00H WDTEN Control WDT Opera...

Страница 121: ...be so alive that WT can continue the operation The watch timer counter circuits may be composed of 21 bit counter which contains low 14 bit with binary counter and high 7 bit counter in order to raise...

Страница 122: ...can control the clock source WTCK 1 0 interrupt interval WTIN 1 0 and function enable disable WTEN Also there is WT interrupt flag bit WTIFR 11 4 5 Register Description for Watch Timer WTCNT Watch Ti...

Страница 123: ...t becomes 1 For clearing bit write 0 to this bit or automatically clear by software Writing 1 has no effect 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval...

Страница 124: ...nternal or an external clock source ECn The clock source is selected by clock selection logic which is controlled by the clock selection bits TnCK 2 0 TIMER 0 1 2 3 clock source fX 2 4 8 32 128 512 20...

Страница 125: ...ing edge If the ECn is selected as a clock source by TnCK 2 0 EC0 EC1 EC2 EC3 port should be set to the input port by P54IO P55IO P56IO P57IO bit P r e s c a l e r fx M U X fx 2 TnCNT 8Bit ECn fx 4 fx...

Страница 126: ...er 0 1 2 3 occurs In PWM mode the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H The timer 0 1 2 3 overflow interrupt...

Страница 127: ...H FFH FEH 00H Tn Match Interrupt Tn Overflow Interrupt TnDR 1 TnDR 4AH Timer n clock Set TnEN TnPWM Tn Match Interrupt 2 TnDR 00H TnPWM Tn Match Interrupt 3 TnDR FFH PWM Mode TnMS 01b Figure 11 9 PWM...

Страница 128: ...vailable According to EIPOL1H L registers setting the external interrupt EINT1n function is chosen Of course the EINT1n pin must be set to an input port TnCDR and TnDR are in the same address In the c...

Страница 129: ...flow in Capture Mode Where n 0 1 2 and 3 TnCNT Interrupt Request FLAG1n XXH Interrupt Interval Period FFH 01H FFH 01H YYH 01H Ext EINT1n PIN Interrupt Request TnIFR FFH FFH YYH 00H 00H 00H 00H 00H TnC...

Страница 130: ...ounter TnDR 8Bit Comparator TnIFR TnO PWMnO 8 bit Timer n Data Register TnCC Clear Match signal Match MUX TnCDR 8Bit Clear TnOVIFR To interrupt block EINT1n POL1n of EIPOL1L FLAG1n EIFLAG1 n To interr...

Страница 131: ...3 capture data register TnCDR timer 0 1 2 3 control register TnCR timer interrupt control register TINTCR and timer interrupt flag register TIFLAG0 11 5 6 2 Register Description for Timer Counter 0 1...

Страница 132: ...mer counter mode 0 1 PWM mode 1 x Capture mode TnCK 2 0 Select Timer n clock source fx is a system clock frequency TnCK2 TnCK1 TnCK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1 fx 32 1 0 0 fx 1...

Страница 133: ...le or Disable Timer 2 Match Interrupt 0 Disable 1 Enable T1MIE Enable or Disable Timer 1 Match Interrupt 0 Disable 1 Enable T0MIE Enable or Disable Timer 0 Match Interrupt 0 Disable 1 Enable T3OVIE En...

Страница 134: ...occurs this bit becomes 1 The flag is cleared only by writing a 0 to the bit So the flag should be cleared by software Writing 1 has no effect 0 T2 interrupt no generation 1 T3 interrupt generation T...

Страница 135: ...so Timer 4 5 outputs PWM wave form through PWMnO port in the PPG mode Table 11 7 Timer 4 5 Operating Modes TnEN TnMS 1 0 TnCK 2 0 Timer 4 5 1 00 XXX 16 Bit Timer Counter Mode 1 01 XXX 16 Bit Capture M...

Страница 136: ...atch Buffer Register A A Match TnCC Reload Pulse Generator TnO R TnEN 3 TnCK 2 0 2 TnMS1 TnMS0 TnCC 0 0 X TnCK2 TnCRL X ADDRESS CAH D2H INITIAL VALUE 0000_0000B TnCK1 TnCK0 TnIFR TnPOL TnECE TnCNTR X...

Страница 137: ...to EIPOL1H registers setting the external interrupt EINT1n function is chosen Of course the EINT1n pin must be set as an input port A Match TnCC TnEN P r e s c a l e r fx M U X fx 2 fx 4 fx 64 fx 512...

Страница 138: ...pture Mode where n 4 and 5 TnCNTH L Interrupt Request FLAG1n XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT1n PIN Interrupt Request TnIFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H TnCNTH...

Страница 139: ...048 fx 8 fx 1 Comparator 16 bit Counter TnCNTH TnCNTL 16 bit B Data Register TnBDRH TnBDRL Clear B Match Edge Detector TnECE ECn Buffer Register B Comparator 16 bit A Data Register TnADRH TnADRL TnIFR...

Страница 140: ...TnADRH L PWMnO A Match 2 TnBDRH L TnADRH L PWMnO A Match 3 TnBDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer n clock Counter TnADRH L Tn Interrupt PWMnO B Match One shot Mode TnMS 10b and Start High...

Страница 141: ...r fx M U X fx 4 fx 8 fx 512 fx 2048 fx 64 fx 2 Edge Detector TnECE ECn fx 1 To other block TnCK 2 0 3 A Match TnCC TnEN A Match TnCC TnEN TnIFR INT_ACK Clear To interrupt block Figure 11 21 16 Bit Tim...

Страница 142: ...R W R W Initial value FFH TnADRH 7 0 Tn A Data High Byte TnADRL Timer n A Data Low Register CCH D4H n 4 and 5 7 6 5 4 3 2 1 0 TnADRL7 TnADRL6 TnADRL5 TnADRL4 TnADRL3 TnADRL2 TnADRL1 TnADRL0 R W R W R...

Страница 143: ...disable 1 Timer n enable Counter clear and start TnMS 1 0 Control Timer n Operation Mode TnMS1 TnMS0 Description 0 0 Timer counter mode TnO toggle at A match 0 1 Capture mode The A match interrupt ca...

Страница 144: ...l clock ECn TnIFR When Tn Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 Tn Interrupt no generation 1 Tn Interrupt g...

Страница 145: ...imer 6 7 8 9 outputs PWM wave form through PWMnO port in the PPG mode Table 11 9 Timer 6 7 8 9 Operating Modes TnEN TnMS 1 0 TnCK 2 0 Timer 6 7 8 9 1 00 XXX 16 Bit Timer Counter Mode 1 01 XXX 16 Bit C...

Страница 146: ...r Register A A Match TnCC Reload Pulse Generator TnO R TnEN 3 TnCK 2 0 2 TnMS1 TnMS0 TnCC 0 0 X TnCK2 TnCRL X ADDRESS DAH E2H EAH 1058H INITIAL VALUE 0000_0000B TnCK1 TnCK0 TnIFR TnPOL TnECE TnCNTR X...

Страница 147: ...and EIPOL2H registers setting the external interrupt EINT1n function is chosen Of course the EINT1n pin must be set as an input port A Match TnCC TnEN P r e s c a l e r fx M U X fx 2 fx 4 fx 64 fx 512...

Страница 148: ...Capture Mode where n 6 7 8 and 9 TnCNTH L Interrupt Request FLAG1n XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT1n PIN Interrupt Request TnIFR FFFFH FFFFH YYH 00H 00H 00H 00H 00H...

Страница 149: ...fx 8 fx 1 Comparator 16 bit Counter TnCNTH TnCNTL 16 bit B Data Register TnBDRH TnBDRL Clear B Match Edge Detector TnECE ECn Buffer Register B Comparator 16 bit A Data Register TnADRH TnADRL TnIFR S...

Страница 150: ...DRH L PWMnO A Match 2 TnBDRH L TnADRH L PWMnO A Match 3 TnBDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer n clock Counter TnADRH L Tn Interrupt PWMnO B Match One shot Mode TnMS 10b and Start High TnP...

Страница 151: ...ge Detector TnECE ECn fx 1 To other block TnCK 2 0 3 To interrupt block TnMIE A Match TnCC TnEN A Match TnCC TnEN Figure 11 29 16 Bit Timer 6 7 8 9 Block Diagram where n 6 7 8 and 9 11 7 6 Register Ma...

Страница 152: ...W R W R W R W Initial value FFH TnADRH 7 0 Tn A Data High Byte TnADRL Timer n A Data Low Register DCH E4H ECH 105AH SFR SFR SFR XSFR n 6 7 8 and 9 7 6 5 4 3 2 1 0 TnADRL7 TnADRL6 TnADRL5 TnADRL4 TnADR...

Страница 153: ...le or Disable Timer n Match Interrupt 0 Disable 1 Enable TnMS 1 0 Control Timer n Operation Mode TnMS1 TnMS0 Description 0 0 Timer counter mode TnO toggle at A match 0 1 Capture mode The A match inter...

Страница 154: ...Description 0 0 0 fx 2048 0 0 1 fx 512 0 1 0 fx 64 0 1 1 fx 8 1 0 0 fx 4 1 0 1 fx 2 1 1 0 fx 1 1 1 1 External clock ECn TnPOL TnO PWMnO Polarity Selection 0 Start High TnO PWMnO is low level at disab...

Страница 155: ...es 1 The flag is cleared only by writing a 0 to the bit So the flag should be cleared by software Writing 1 has no effect 0 T8 interrupt no generation 1 T8 interrupt generation T7IFR When T7 interrupt...

Страница 156: ...ivided by prescaler Table 11 11 Buzzer Frequency at fBUZ 2 MHz BUZDR 5 0 Buzzer Frequency kHz BUZDIV 1 0 00 BUZDIV 1 0 01 BUZDIV 1 0 10 BUZDIV 1 0 11 00_0000 125kHz 62 5kHz 31 25kHz 15 625kHz 00_0001...

Страница 157: ...driver consists of buzzer data register BUZDR and buzzer control register BUZCR 11 8 5 Register Description for Buzzer Driver BUZDR Buzzer Data Register F3H 7 6 5 4 3 2 1 0 BUZDIV1 BUZDIV0 BUZDR5 BUZD...

Страница 158: ...itial value 00H BUCK 2 0 Buzzer Driver Source Clock Selection BUCK2 BUCK1 BUCK0 Description 0 0 0 fx 1 0 0 1 fx 2 0 1 0 fx 4 0 1 1 fx 8 1 0 0 fx 16 1 0 1 fx 32 1 1 0 fx 64 1 1 1 fSUB External Sub OSC...

Страница 159: ...an select serial clock SCK2 3 polarity phase and whether LSB first data transfer or MSB first data transfer 11 9 2 Block Diagram P r e s c a l e r fx M U X fx 4 fx 8 fx 32 fx 64 fx 128 fx 16 fx 2 SCK...

Страница 160: ...en the SPI 2 3 is configured as a Slave the SS2 3 pin is always input If LOW signal come into SS2 3 pin the SPI 2 3 logic is active And if HIGH signal come into SS2 3 pin the SPI 2 3 logic is stop In...

Страница 161: ...SIn Output MOSIn MISOn Input SCKn CPOLn 0 SSn SPInIFR Figure 11 32 SPI 2 3 Transmit Receive Timing Diagram at CPHA 0 Where n 2 and 3 SCKn CPOLn 1 MISOn MOSIn Output MOSIn MISOn Input D0 D1 D2 D3 D4 D5...

Страница 162: ...3 Register Description The SPI 2 3 register consists of SPI 2 3 control register SPInCR SPI 2 3 status register SPInSR and SPI 2 3 data register SPInDR 11 9 8 Register Description for SPI 2 3 SPInDR S...

Страница 163: ...SPI 2 3 Interrupt no generation 1 SPI 2 3 Interrupt generation WCOLn This bit is set if any data are written to the data register SPInDR during transfer This bit is cleared when the status register S...

Страница 164: ...This two bits control the serial clock SCK2 3 mode Clock polarity CPOLn bit determine SCK2 3 s value at idle mode Clcok phase CPHAn bit determine if data are sampled on the leading or trailing edge o...

Страница 165: ...lete UART2 3 4 has baud rate generator transmitter and receiver The baud rate generator for asynchronous operation The Transmitter consists of a single write buffer a serial shift register parity gene...

Страница 166: ...n Tx Control Stop bit Generator M U X UnPM1 Parity Generator Transmit Shift Register TXSR UARTnDR Tx UnPM0 I N T E R N A L B U S L I N E M U X LOOPSn TXCn TXCIEn UDRIEn UDREn Empty signal To interrupt...

Страница 167: ...tes the base clock for the transmitter and receiver Following table shows equations for calculating the baud rate in bps Table 11 14 Equations for Calculating Baud Rate Register Setting Operating Mode...

Страница 168: ...an idle state The idle means high state of data pin The following figure shows the possible combinations of the frame formats Bits inside brackets are optional Figure 11 36 Frame Format 1 data frame c...

Страница 169: ...ansmitter flag and interrupt The UART2 3 4 transmitter has 2 flags which indicate its state One is UART2 3 4 data register empty flag UDREn and the other is transmit complete flag TXCn Both flags can...

Страница 170: ...t before serial reception 11 10 7 1 Receiving Rx data The receiver starts data reception when it detects a valid start bit LOW on RXDn pin Each bit after start bit is sampled at pre defined baud rate...

Страница 171: ...rst stop bit The FEn flag is 0 when the stop bit was correctly detected as 1 and the FE flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync cond...

Страница 172: ...logical low level it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame And the data recovery can begin The synchronization...

Страница 173: ...UARTn Control Register 1 UARTnCR2 1039H 1041H 1049H XSFR R W 00H UARTn Control Register 2 UARTnCR3 103AH 1042H 104AH XSFR R W 00H UARTn Control Register 3 UARTnST 103BH 1043H 104BH XSFR R W 80H UARTn...

Страница 174: ...to the UARTnDR register Reading the UARTnDR register returns the contents of the Receive Buffer Write this register only when the UDREn flag is set UARTnCR1 UARTn Control Register 1 1038H 1040H 1048H...

Страница 175: ...e polling 1 When RXCn is set request an interrupt WAKEIEn Interrupt enable bit for Wake in STOP mode When device is in stop mode if RXDn goes to LOW level an interrupt can be requested to wake up syst...

Страница 176: ...mode 0 Normal operation 1 Loop Back mode USBSn Selects the length of stop bit 0 1 Stop Bit 1 2 Stop Bit UnTX8 The ninth bit of data frame in UARTn Write this bit first before loading the UARTnDR regi...

Страница 177: ...ead The RXCn flag can be used to generate a RXCn interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKEn This flag is set when the RXDn pin i...

Страница 178: ...x 3 6864MHz fx 4 00MHz fx 7 3728MHz UARTnBD ERROR UARTnBD ERROR UARTnBD ERROR 2400 95 0 0 103 0 2 191 0 0 4800 47 0 0 51 0 2 95 0 0 9600 23 0 0 25 0 2 47 0 0 14 4k 15 0 0 16 2 1 31 0 0 19 2k 11 0 0 12...

Страница 179: ...register USI0 1 SDA hold time register USI0 1 SCL high period register USI0 1 SCL low period register and USI0 1 slave address register USInCR1 USInCR2 USInCR3 USInCR4 USInST1 USInST2 USInBD USInDR U...

Страница 180: ...generator Transmitter and receiver The clock generation logic consists of synchronization logic for external clock input used by synchronous or SPI slave operation and the baud rate generator for asy...

Страница 181: ...Register TXSR USInDR USInTX8 Tx USInP 1 0 M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn RXCIEn WAKEIEn WAKEn At Stop mode To interrupt block SCLK fx System clo...

Страница 182: ...hronous operation Asynchronous double speed mode is controlled by the DBLSn bit in the USInCR2 register The MASTERn bit in USInCR3 register controls whether the clock source is internal master mode ou...

Страница 183: ...hronous or SPI mode is used the SCKn pin will be used as either clock input slave or clock output master Data sampling and transmitter is issued on the different edge of SCKn clock each other For exam...

Страница 184: ...ate The idle means high state of data pin The following figure shows the possible combinations of the frame formats Bits inside brackets are optional Figure 11 43 Frame Format USI0 1 1 data frame cons...

Страница 185: ...t in USInCR3 register before it is loaded to the transmit buffer USInDR register 11 11 9 2 USI0 1 UART Transmitter flag and interrupt The UART transmitter has 2 flags which indicate its state One is U...

Страница 186: ...in in slave mode or can be configured as SSn output pin in master mode This can be done by setting USInSSEN bit in USnCR3 register 11 11 10 1 USI0 1 UART Receiving Rx data When UART is in synchronous...

Страница 187: ...FEn flag is 0 when the stop bit was correctly detected as 1 and the FEn flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync conditions between d...

Страница 188: ...e logical low level it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame And the data recovery can begin The synchronizatio...

Страница 189: ...ted else a frame error FEn flag is set After deciding whether the first stop bit is valid or not the Receiver goes to idle state and monitors the RXDn line to check a valid high to low transition is d...

Страница 190: ...patibility to other SPI devices 11 11 12 USI0 1 SPI Clock Formats and Timing To accommodate a wide variety if synchronous serial peripherals from different manufacturers the USI0 1 has a clock polarit...

Страница 191: ...MOSIn inputs respectively At the second SCKn edge the USI0 1 shifts the second data bit value out to the MOSIn and MISOn outputs of the master and slave respectively Unlike the case of CPHAn 1 when CP...

Страница 192: ...ut to the MOSIn and MISOn output of the master and slave respectively When CPHAn 1 the slave s SSn input is not required to go to its inactive high level between transfers Because the SPI logic reuses...

Страница 193: ...T E R N A L B U S L I N E M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn Baud Rate Generator USInBD TXEn SCLK fx System clock MISOn MOSIn M U X MASTERn D E P F...

Страница 194: ...andard Multi master operation Up to 400kHz data transfer read speed 7 bit address Both master and slave operation Bus busy detection 11 11 15 USI0 1 I2C Bit Transfer The data on the SDAn line must be...

Страница 195: ...conditions are functionally identical Figure 11 51 START and STOP Condition USIn where n 0 and 1 11 11 17 USI0 1 I2C Data Transfer Every byte put on the SDAn line must be 8 bits long The number of by...

Страница 196: ...here n 0 and 1 11 11 19 USI0 1 I2C Synchronization Arbitration Clock synchronization is performed using the wired AND connection of I2C interfaces to the SCLn line This means that a HIGH to LOW transi...

Страница 197: ...USInCR4 register is set it is cleared by writing an any value to USInST2 When I2C interrupt occurs the SCLn line is hold LOW until writing any value to USInST2 When the IICnIFR flag is set the USInST2...

Страница 198: ...he following cases regardless of the reception of ACK signal from slave 1 Master receives ACK signal from slave so continues data transfer because slave can receive more data from master In this case...

Страница 199: ...r Data Write From slave to master 0xxx Value of Status Register ACK Interrupt SCLn line is held low Interrupt after stop command P Arbitration lost as master and addressed as slave LOST Other master c...

Страница 200: ...owing steps continue assuming that I2C does not lose mastership during first data transfer I2C Master can choose one of the following cases according to the reception of ACK signal from slave 1 Master...

Страница 201: ...as the following figure Figure 11 57 Formats and States in the Master Receiver Mode USIn where n 0 and 1 From master to slave Master command or Data Write From slave to master 0xxx Value of Status Re...

Страница 202: ...s for another START condition Else if the address equals to USInSLA 6 0 bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equ...

Страница 203: ...r Mode USIn where n 0 and 1 SLA R ACK DATA LOST S or Sr Y 0x47 ACK STOP Y N 0x46 P 0x22 IDLE IDLE Y GCALL 0x1F 0x97 0x17 From master to slave Master command or Data Write From slave to master 0xxx Val...

Страница 204: ...nother START condition Else if the address equals to SLAn bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to SLAn bi...

Страница 205: ...ver Mode USIn where n 0 and 1 SLA W ACK DATA LOST S or Sr Y N 0x45 ACK STOP Y N 0x44 P 0x20 IDLE IDLE Y GCALL 0x1D 0x95 0x15 From master to slave Master command or Data Write From slave to master 0xxx...

Страница 206: ...ss Register USInSAR General Call And Address Detector USInGCE STOP START Condition Generator STOPCn STARTCn ACK Signal Generator ACKnEN RXACKn GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn Interrupt G...

Страница 207: ...XSFR R W 00H USIn Status Register 2 11 11 23 USI0 1 Register Description USI0 1 module consists of USI0 1 baud rate generation register USInBD USI0 1 data register USInDR USI0 1 SDA hold time register...

Страница 208: ...0 The register is used to control SDAn output timing from the falling edge of SCLn in I2C mode NOTE that SDA is changed after tSCLK X USInSDHR In master mode load half the value of USInSCLR to this re...

Страница 209: ...K the system clock and the period is calculated by the formula tSCLK X 4 X USInSCLR 2 where tSCLK is the period of SCLK USInSAR USI0 1 Slave Address Register For I2C mode 1027H 1037H XSFR n 0 1 7 6 5...

Страница 210: ...length of data bits in frame USInS2 USInS1 USInS0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit ORDn This bit in the same bit po...

Страница 211: ...om RXCn is inhibited use polling 1 When RXCn is set request an interrupt WAKEIEn Interrupt enable bit for asynchronous wake in STOP mode When device is in stop mode if RXDn goes to low level an interr...

Страница 212: ...ile UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring USInSSEN This bit controls the SSn pin operation only SPI mode 0 Disable 1 Enable The SSn pin should b...

Страница 213: ...bit for I2C mode 0 Interrupt from I2C is inhibited use polling 1 Enable interrupt for I2C ACKnEN Controls ACK signal Generation at ninth SCL period 0 No ACK signal is generated SDA 1 1 ACK signal is...

Страница 214: ...generate a RXCn interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKEn This flag is set when the RXDn pin is detected low while the CPU is i...

Страница 215: ...t is set when a STOP condition is detected 0 No STOP condition is detected 1 STOP condition is detected SSELn NOTE This bit is set when I2C is addressed by other master 0 I2C is not selected as a slav...

Страница 216: ...Rate fx 3 6864MHz fx 4 00MHz fx 7 3728MHz USI0BD USI1BD ERROR USI0BD USI1BD ERROR USI0BD USI1BD ERROR 2400 95 0 0 103 0 2 191 0 0 4800 47 0 0 51 0 2 95 0 0 9600 23 0 0 25 0 2 47 0 0 14 4k 15 0 0 16 2...

Страница 217: ...set to xx The register ADCDRH and ADCDRL contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCDRH and ADCDRL the A D conversion status bit AFLAG...

Страница 218: ...IFR AFLAG INT_ACK Clear Clear To interrupt block MUX VDD Start M U X T7 match signal T8 match signal T9 match signal REFSEL TRIG 2 0 3 T4 match signal T5 match signal T6 match signal M U X fx 2 fx 4 f...

Страница 219: ...CO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCO11 ADCO10 ADCO9 ADC...

Страница 220: ...W 00H A D Converter Control Low Register 11 13 6 ADC Register Description The ADC register consists of A D converter data high register ADCDRH A D converter data low register ADCDRL A D converter cont...

Страница 221: ...ADDL8 R R R R R R R R Initial value xxH ADDM 11 4 MSB align A D Converter High Data 8 bit ADDL 11 8 LSB align A D Converter High Data 4 bit ADCDRL A D Converter Data Low Register 1052H XSFR 7 6 5 4 3...

Страница 222: ...eration 1 ADC Interrupt generation TRIG 2 0 A D Trigger Signal Selection The ADC module is automatically disabled at stop mode TRIG2 TRIG1 TRIG0 Description 0 0 0 ADST 0 0 1 Timer 4 match signal 0 1 0...

Страница 223: ...signal generation for conversion start REFSEL A D Converter Reference Selection 0 Internal Reference VDD 1 External Reference AVREF AFLAG A D Converter Operation State This bit is cleared to 0 when t...

Страница 224: ...r Operates Continuously Stop Can be operated with sub clock Timer0 9 Operates Continuously Halted Only when the Event Counter Mode is Enabled Timer operates Normally ADC Operates Continuously Stop BUZ...

Страница 225: ...nd peripherals are operated normally but CPU stops It is released by reset or interrupt To be released by interrupt interrupt should be enabled before IDLE mode If using reset because the device becom...

Страница 226: ...lock The source for exit from STOP mode is hardware reset and interrupts The reset re defines all the control registers When exit from STOP mode enough oscillation stabilization time is required to no...

Страница 227: ...STOP mode is released by the interrupt which each interrupt enable flag 1 and the CPU jumps to the relevant interrupt service routine Even if the IE EA bit is cleared to 0 the STOP mode is released by...

Страница 228: ...N Power Control Register 87H 7 6 5 4 3 2 1 0 PCON7 PCON3 PCON2 PCON1 PCON0 R W R W R W R W R W Initial value 00H PCON 7 0 Power Control 01H IDLE mode enable 03H STOP mode enable Other Values Normal op...

Страница 229: ...ripheral Registers 13 2 Reset Source The MC97F2664 has five types of reset sources The following is the reset sources External RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN 1 Low V...

Страница 230: ...wer the POR Power On Reset has a function to reset the device If POR is used it executes the device RESET function instead of the RESET IC or the RESET circuits Figure 13 3 Fast VDD Rising Time Figure...

Страница 231: ...Read POR VDD Input Internal OSC VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 16MHz 16 INT OSC 16MHz RESET_SYSB Config Read 1us X 256 X 28h about 10ms 1us X 4096 X 4h ab...

Страница 232: ...st rise over than flash operating voltage for Config read Slew Rate 0 15V ms Config read point about 1 5V 1 6V Config Value is determined by Writing Option Rising section to Reset Release Level 16ms p...

Страница 233: ...te the internal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure 13 7 Timing Diagram after RESET F...

Страница 234: ...2 59V 2 75V 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the LVREN bit is set to off...

Страница 235: ...75V LVI Circuit LVILS 3 0 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V 2 10V 2 20V 2 32V 2 00V 4 Figure 13 12 LVI Diagram VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 16MHz 16 I...

Страница 236: ...it The bit is reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection WDTRF Watch Dog Reset flag bit The bit is reset by writing 0 to this bit or by Power On Reset 0 No detectio...

Страница 237: ...his bit is 0 the LVREN bit is not effect by stop mode to release LVRVS 3 0 LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 0 0 0 0 1 60V 0 0 0 1 2 00V 0 0 1 0 2 10V 0 0 1 1 2 20V 0 1 0 0 2...

Страница 238: ...LVIF Low Voltage Indicator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVILS 3 0 LVI Level Select LVILS3 LVILS2 LVILS1 LVILS0 Description 0 0 0 0 2 00V 0 0 0 1 2 10...

Страница 239: ...bus Debugger Access to All Internal Peripheral Units Internal data RAM Program Counter Flash and Data EEPROM Memories Extensive On chip Debug Support for Break Conditions Including Break Instruction S...

Страница 240: ...it as 0 when transmission for 8 bit data and its parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When acknowledge e...

Страница 241: ...Data Transfer on the Twin Bus 14 2 2 2 Bit Transfer Figure 14 4 Bit Transfer on the Serial Bus data line stable data valid except Start and Stop change of data allowed DSDA DSCL St Sp START STOP DSDA...

Страница 242: ...tart and Stop Condition 14 2 2 4 Acknowledge Bit Figure 14 6 Acknowledge on the Serial Bus 1 9 2 10 Data output by transmitter Data output By receiver DSCL from master clock pulse for acknowledgement...

Страница 243: ...ronization during Wait Procedure Start wait start HIGH Host PC DSCL OUT Target Device DSCL OUT DSCL wait HIGH Maximum 5 TSCLK Internal Operation Acknowledge bit transmission minimum 1 TSCLK for next b...

Страница 244: ...ction of Transmission DSCL OUT DSDA OUT DSDA IN DSCL Debugger Serial Clock Line DSDA Debugger Serial Data Line DSDA OUT DSDA IN Host Machine Master Target Device Slave VDD Current source for DSCL to f...

Страница 245: ...while mounted on the board The flash memory can be read by MOVC instruction and it can be programmed in OCD2 serial ISP mode or user program mode Flash Size 64k bytes Single power supply program and e...

Страница 246: ...0H 0FF7FH 0FF40H Sector 1021 0FF40H 0FF3FH Sector 1020 Sector 2 00080H 0007FH 00040H Sector 1 00040H 0003FH 00000H Sector 0 00000H 00080H 8000H Flash Page Buffer External Data Memory 64bytes 803FH ROM...

Страница 247: ...Low Register FIDR FDH R W 00H Flash Identification Register FMCR FEH R W 00H Flash Mode Control Register 15 1 4 Register Description for Flash Memory Control and Status Flash control register consists...

Страница 248: ...0 Flash Sector Address Middle FSADRL Flash Sector Address Low Register FCH 7 6 5 4 3 2 1 0 FSADRL7 FSADRL6 FSADRL5 FSADRL4 FSADRL3 FSADRL2 FSADRL1 FSADRL0 R W R W R W R W R W R W R W R W Initial valu...

Страница 249: ...errupt is on disable state regardless of the IE 7 EA bit FMCR2 FMCR1 FMCR0 Description 0 0 1 Select flash page buffer reset mode and start regardless of the FIDR value Clear all 32bytes to 0 0 1 0 Sel...

Страница 250: ...re available only when the PAEN bit is cleared to 0 that is enable protection area at the configure option 2 if it is needed If the protection area isn t enabled PAEN 1 this area can be used as a norm...

Страница 251: ...NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 64 Sector size is 64bytes MOV DPH 0x80 MOV DPL 0 Pgbuf_clr MOVX DPTR A INC DPTR DJNZ R0 Pgbuf_clr Write 0 to all page buffer MOV F...

Страница 252: ...ummy instruction This instruction must be needed MOV A 0 MOV DPH 0x80 MOV DPL 0 MOVX DPTR A MOV DPH 0x80 MOV DPL 0x05 MOVX DPTR A Write 0 to page buffer MOV FSADRH 0x00 MOV FSADRM 0x7F MOV FSADRL 0x40...

Страница 253: ...This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 64 Sector size is 64bytes MOV DPH 0x80 MOV DPL 0 Pgbuf_WR MOVX DPTR A INC A INC DPTR DJNZ R0 Pgbuf...

Страница 254: ...must be needed NOP Dummy instruction This instruction must be needed MOV A 5 MOV DPH 0x80 MOV DPL 0 MOVX DPTR A Write data to page buffer MOV A 6 MOV DPH 0x80 MOV DPL 0x05 MOVX DPTR A Write data to pa...

Страница 255: ...ddress MOVC A A DPTR read data from flash memory 15 1 11 Hard Lock Mode The Reading program procedure in user program mode 1 Set flash identification register FIDR 2 Set flash mode control register FM...

Страница 256: ...tor Area 00H FFH Protection Enable Disable 0 Disable Protection Erasable by instruction 1 Enable Protection Not erasable by instruction RSTS RESETB Select 0 P57 EC3 port 1 RESETB port with a pull up r...

Страница 257: ...UBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 07 DEC...

Страница 258: ...t byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 F7 MOV Ri dir Move direct byte to ind...

Страница 259: ...2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare i...

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