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A96G150 User's manual

15. Combination of USART, SPI, and I2C (USI)

187

The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate
is 16 times of the baud-rate in normal mode and 8 times the baud-rate for double speed mode
(DBLSn=1). The horizontal arrows show the synchronization variation due to the asynchronous
sampling process. Note that larger time variation is shown when using the double speed mode.

Figure 84. Asynchronous Start Bit Sampling (USIn)

When the receiver is enabled (RXEn=1), the clock recovery logic tries to find a high-to-low transition on
the RXDn line, the start bit condition. After detecting high to low transition on RXDn line, the clock
recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received. If more
than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally
generated clock is synchronized to the incoming data frame. And the data recovery can begin. The
synchronization process is repeated for each start bit.

As described above, when the receiver clock is synchronized to the start bit, the data recovery can
begin. Data recovery process is almost same to the clock recovery process. The data recovery logic
samples 16 times for each incoming bits for normal mode and 8 times for double speed mode, and uses
sample 8, 9 and 10 to decide data value. If more than 2 samples have low levels, the received bit is

considered to a logic ‘0’ and if more than 2 samples have high le

vels, the received bit is considered to

a logic

‘1’.

RXDn

0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

1

2

3

IDLE

BIT0

START

0

1

2

3

4

5

6

7

8

1

2

Sample

(DBLSn = 0)

Sample

(DBLSn = 1)

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Содержание A96G150

Страница 1: ...er highly flexible and cost effective solutions 64Kbytes of FLASH 256bytes of IRAM 2304bytes of XRAM 2Kbytes of Data EEPROM general purpose I O basic interval timer watchdog timer 8 16 bit timer count...

Страница 2: ...6 1 Port register 48 6 1 1 Data register Px 48 6 1 2 Direction register PxIO 48 6 1 3 Pull up register selection register PxPU 48 6 1 4 Open drain selection register PxOD 48 6 1 5 De bounce enable reg...

Страница 3: ...r description 83 8 Clock generator 89 8 1 Clock generator block diagram 90 8 2 Register map 91 8 3 Register description 92 9 Basic Interval Timer BIT 94 9 1 BIT block diagram 94 9 2 BIT register map 9...

Страница 4: ...5 12 6 1 16 bit timer counter mode 156 12 6 2 16 bit capture mode 158 12 6 3 16 bit PPG mode 160 12 6 4 16 bit timer 5 block diagram 162 12 6 5 Register map 162 12 6 6 Register description 163 13 Buzz...

Страница 5: ...2 15 19 3USIn I2C slave transmitter 204 15 19 4USIn I2C slave receiver 205 15 20 USIn I2C block diagram 207 15 21 Register map 208 15 22 USIn register description 209 15 23 Baud rate settings example...

Страница 6: ...2 Power on reset 272 20 3 External resetb input 275 20 4 Low voltage reset process 276 20 5 LVI block diagram 278 20 6 Register map 279 20 7 Reset operation register description 280 21 Memory program...

Страница 7: ...ng debug mode 316 22 3 3 Two wire communication protocol 317 22 4 Programmers 321 22 4 1 E PGM 321 22 4 2 OCD emulator 321 22 4 3 Gang programmer 322 22 5 Flash programming 323 22 5 1 On board program...

Страница 8: ...am 94 Figure 23 Watchdog Timer Interrupt Timing Waveform 97 Figure 24 Watchdog Timer Block Diagram 98 Figure 25 Watch Timer Block Diagram 101 Figure 26 8 bit Timer Counter Mode for Timer 0 106 Figure...

Страница 9: ...1 16 bit PPG Mode of Timer 5 160 Figure 72 16 bit PPG Mode Operation Example 161 Figure 73 16 bit Timer 5 Block Diagram 162 Figure 74 Buzzer Driver Block Diagram 165 Figure 75 12 bit ADC Block Diagram...

Страница 10: ...igure 122 Internal RESET Release Timing on Power up 272 Figure 123 Configuration Timing when Power on 273 Figure 124 Boot Process Waveform 274 Figure 125 Timing Diagram after RESET 275 Figure 126 Osci...

Страница 11: ...al Bus 320 Figure 150 Clock Synchronization during Wait Procedure 320 Figure 151 E PGM Single Writer and Pinouts 321 Figure 152 E Gang4 and E Gang6 for Mass Production 322 Figure 153 Connection of Tra...

Страница 12: ...IMER 5 Register Map 162 Table 26 Buzzer Frequency at 8MHz 165 Table 27 Buzzer Driver Register Map 166 Table 28 ADC Register Map 172 Table 29 Equations for Calculating USIn Baud Rate Register Setting 1...

Страница 13: ...e and Debug Interface by Series 308 Table 54 Feature Comparison Chart by Series and Cores 309 Table 55 OCD Type of Each Series 310 Table 56 Comparison of OCD 1 and OCD 2 310 Table 57 Interrupt Priorit...

Страница 14: ...M8051 2 clocks per cycle Interrupt Up to 23 peripheral interrupts supported EINT40 to 47 EINT0 EINT1 EINT2 EINT3 5 Timer 0 1 2 3 4 5 6 WDT 1 BIT 1 WT 1 USART Rx CRC Tx 2 USI 2 ch Rx Tx I2C 6 ADC 1 LV...

Страница 15: ...32 768 kHz Timer counter Basic interval timer BIT 8 bit x 1 ch Watchdog timer WDT 8 bit x 1 ch 8 bit x 1 ch T0 16 bit x 5 ch T1 T2 T3 T4 T5 Communication function USART2 8 bit USART x 1 ch or 8 bit S...

Страница 16: ...tor HSI 32MHz 2 0 TA 40 85 C HSI 32MHz 3 0 TA 40 105 C LSI 128kHz 20 TA 40 85 C LSI 128kHz 30 TA 40 105 C Operating voltage and frequency LVR 1 8V to 5 5V 32 768KHz with crystal 2 4V to 5 5V 4MHz to 1...

Страница 17: ...2MHz Crystal OSC 32 768kHz Crystal OSC Buzzer 1 channel 8 bit UART 3 channels 8 bit SPI 3 channels 8 bit I2C 2 channels 8 bit CORE M8051 General purpose I O 42 ports normal I O Watchdog timer 1 channe...

Страница 18: ...18 2 Pinouts and pin description In this chapter A96G150 device pinouts and pin descriptions are introduced 2 1 Pinouts A96G150SN 44 LQFP NOTE The programmer E PGM E Gang4 6 uses P1 3 P1 1 pin as DSC...

Страница 19: ...ut LCD_S18 O LCD Segment Signal 18 Output T1O O Timer 1 interval output PWM1O O Timer 1 PWM output 2 P03 IOUS Port 0 bit 3 Input output T0O O Timer 0 interval output PWM0O O Timer 0 PWM output 3 P04 I...

Страница 20: ...SART1 clock signal 30 P13 IOUS Port 1 bit 3 Input output LCD_S3 O LCD Segment Signal 3 Output EINT47 I External interrupt input ch 47 TXD1 O USART1 data transmit SDA1 IO I2C1 data signal MOSI1 IO USAR...

Страница 21: ...T1 data receive SCL1 IO I2C1 clock signal MISO1 IO USART1 SPI MISO 38 P23 IOU Port 2 bit 3 Input output LCD_S11 O LCD Segment Signal 11 Output TXD1 O USART1 data transmit SDA1 IO I2C1 data signal MOSI...

Страница 22: ...put LED_C3 O High sink current ports LCD_C3 O LCD Common Signal 3 Output AN9 IA ADC input ch 9 22 P34 IOUS Port 3 bit 4 Input output LED_C4 O High sink current ports LCD_C4 O LCD Common Signal 4 Outpu...

Страница 23: ...output EINT42 I External interrupt input ch 42 AN2 IA ADC input ch 2 VLC2 IA External LCD Voltage bias 2 SS2 IO USART2 slave select signal 15 P43 IOUS Port 4 bit 3 Input output EINT43 I External inte...

Страница 24: ...d as one of the P52 and RESETB pin by the CONFIGURE OPTION 2 If the P11 LCD_S1 EINT45 AN14 DSDA and P13 LCD_S3 EINT47 DSCL pins are connected to the programmer during power on reset the pins are autom...

Страница 25: ...vely PULL UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB FUNC DATA OUTPUT SUB FUNC ENABLE DIRECTION REGISTER SUB FUNC DIRECTION Q D r CP DEBOUNCE CLK DEBOUNCE ENABLE SUB FUNC DATA INPUT PORTx INPUT...

Страница 26: ...DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r D CP Q DEBOUNCE CLK DEBOUNCE ENABLE PORTx INPUT SUB FUNC DATA I...

Страница 27: ...times the speed at the same power consumption or to use one sixth of the power when running at the standard speed All instructions have zero wait state execution times that are exactly 1 6 those of t...

Страница 28: ...nous and asynchronous Program External Data Internal Data Memory Wait states support for slow Program and External Data Memory 16 bit Data Memory address is generated through the DPTR Data Point regis...

Страница 29: ...our banks of registers are available The current bank is selected by bits 3 and 4 of the PSW Register specific addressing Some instructions only operate on specific registers This is defined by the op...

Страница 30: ...sed in most addressing modes There are seven accumulator specific instructions CLR A Clear A CPL A Complement A RL A Rotate Left A RLC A Rotate Left through Carry A RR A Rotate Right A RRC A Rotate Ri...

Страница 31: ...ll conditional jump instructions use relative addressing so they are limited to the range of 128 to 127 bytes Boolean Instructions The bit addressable registers in both direct and SFR space may be man...

Страница 32: ...ytes program memory space Figure 6 shows a map of the lower part of the program memory After reset CPU begins execution from location 0000H Each interrupt is assigned a fixed location in the program m...

Страница 33: ...A96G150 User s manual 5 Memory organization 33 FFFFH 0000H 64KB FLASH 7FFFH 32KB FLASH NOTE The 64Kbytes includes the Interrupt Vector Region Figure 6 Program Memory Map...

Страница 34: ...into 4 banks of 8 registers Program instructions call out these registers as R0 through R7 Two bits in the Program Status Word select which register bank is in use This allows more efficient use of c...

Страница 35: ...5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C...

Страница 36: ...bytes of XRAM and XSFR This area has no relation with RAM FLASH It can be read and written to through SFR with 8 bit unit External RAM 2304bytes Indirect Addressing 0000H 08FFH 37FFH 1000H EEPROM Area...

Страница 37: ...0D8H LVRCR USI0CR1 USI0CR2 USI0CR3 USI0CR4 USI0SAR P0DB P14DB 0D0H PSW P5IO P0FSRL P0FSRH P1FSRL P1FSRH P2FSRL P2FSRH 0C8H OSCCR P4IO UCTRL1 UCTRL2 UCTRL3 USTAT 0C0H EIFLAG0 P3IO T2CRL T2CRH T2ADRL T2...

Страница 38: ...7 LCD_DR18 LCD_DR19 LCD_DR20 LCD_DR21 LCD_DR22 LCD_DR23 1058H LCD_DR8 LCD_DR9 LCD_DR10 LCD_DR11 LCD_DR12 LCD_DR13 LCD_DR14 LCD_DR15 1050H LCD_DR0 LCD_DR1 LCD_DR2 LCD_DR3 LCD_DR4 LCD_DR5 LCD_DR6 LCD_DR...

Страница 39: ...val Timer Counter Register BITCNT R 0 0 0 0 0 0 0 0 8DH Watch Dog Timer Control Register WDTCR R W 0 0 0 0 0 8EH Watch Dog Timer Data Register WDTDR W 1 1 1 1 1 1 1 1 Watch Dog Timer Counter Register...

Страница 40: ...ion Register P0PU R W 0 0 0 0 0 0 0 0 ADH P1 Pull up Resistor Selection Register P1PU R W 0 0 0 0 0 0 0 0 AEH P2 Pull up Resistor Selection Register P2PU R W 0 0 0 0 0 0 0 0 AFH P3 Pull up Resistor Se...

Страница 41: ...CTRL3 R W 0 0 0 0 0 0 0 CFH USART Status Register USTAT R W 1 0 0 0 0 0 0 0 D0H Program Status Word Register PSW R W 0 0 0 0 0 0 0 0 D1H P5 Direction Register P5IO R W 0 0 0 0 D2H P0 Function Selectio...

Страница 42: ...I1CR4 R W 0 0 0 0 0 EDH USI1 Slave Address Register USI1SAR R W 0 0 0 0 0 0 0 0 EEH P3 Function Selection Low Register P3FSRL R W 0 0 0 0 0 0 0 0 EFH P3 Function Selection High Register P3FSRH R W 0 0...

Страница 43: ...ister T5CRL R W 0 0 0 0 0 0 1012H Timer 5 A Data High Register T5ADRH R W 1 1 1 1 1 1 1 1 1013H Timer 5 A Data Low Register T5ADRL R W 1 1 1 1 1 1 1 1 1014H Timer 5 B Data High Register T5BDRH R W 1 1...

Страница 44: ...DR6 R W 0 0 0 0 0 0 0 0 1057H LCD Display Data Register 7 LCDDR7 R W 0 0 0 0 0 0 0 0 1058H LCD Display Data Register 8 LCDDR8 R W 0 0 0 0 0 0 0 0 1059H LCD Display Data Register 9 LCDDR9 R W 0 0 0 0 0...

Страница 45: ...ter CRC_MNT_H R W 0 0 0 0 0 0 0 0 1075H CRC Monitor Low Register CRC_MNT_L R W 0 0 0 0 0 0 0 0 1079H CRC Start Address High Register CRC_ADDR_START_H R W 0 107AH CRC Start Address Middle Register CRC_...

Страница 46: ...SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Register Low 82H 7 6 5 4 3 2 1 0 DPL R W R W R W R W R W R W R W R W Initial...

Страница 47: ...er Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P Parity Flag Set Cleared by hardware each instruction cycle to indicate an odd...

Страница 48: ...set 6 1 3 Pull up register selection register PxPU The on chip pull up resistor can be connected to I O ports individually with a pull up resistor selection register PxPU The pull up register selectio...

Страница 49: ...EG option Selection Register P2 90H R W 00H P2 Data Register P2IO B9H R W 00H P2 Direction Register P2PU AEH R W 00H P2 Pull up Resistor Selection Register P2OD 93H R W 00H P2 Open drain Selection Reg...

Страница 50: ...P0IO P0 Direction Register A1H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R W R W R W R W R W R W R W R W Initial value 00H P0IO 7 0 P0 Data I O Direction 0 Input 1 Output NOTES E...

Страница 51: ...ble 1 Enable P06DB Configure De bounce of P06 Port 0 Disable 1 Enable P05DB Configure De bounce of P05 Port 0 Disable 1 Enable P04DB Configure De bounce of P04 Port 0 Disable 1 Enable NOTES 1 If the s...

Страница 52: ...RH4 Description 0 0 I O Port EINT2 function possible when input 0 1 XOUT1 Function 1 0 reserved 1 1 RXD2 Function P0FSRH 3 2 P05 Function Select P0FSRH3 P0FSRH2 Description 0 0 I O Port EINT1 function...

Страница 53: ...6 Description 0 0 I O Port 0 1 reserved 1 0 T0O PWM0O Function 1 1 reserved P0FSRL 5 4 P02 Function Select P0FSRL5 P0FSRL4 Description 0 0 I O Port 0 1 LCD_S18 Function 1 0 T1O PWM1O Function 1 1 rese...

Страница 54: ...I O Data P1IO P1 Direction Register B1H 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R W R W R W R W R W R W R W R W Initial value 00H P1IO 7 0 P1 Data I O Direction 0 Input 1 Outp...

Страница 55: ...of P13 Port 0 Disable 1 Enable P12DB Configure De bounce of P12 Port 0 Disable 1 Enable P11DB Configure De bounce of P11 Port 0 Disable 1 Enable P10DB Configure De bounce of P10 Port 0 Disable 1 Enabl...

Страница 56: ...tion 0 0 I O Port EC3 function possible when input 0 1 LCD_S6 Function 1 0 reserved 1 1 SS0 Function P1FSRH 3 2 P15 Function Select P1FSRH3 P1FSRH2 Description 0 0 I O Port 0 1 LCD_S5 Function 1 0 res...

Страница 57: ...EINT46 function possible when input 0 1 LCD_S2 Function 1 0 reserved 1 1 SCK1 Function P1FSRL 3 2 P11 Function Select P1FSRL3 P1FSRL2 Description 0 0 I O Port EINT45 function possible when input 0 1 L...

Страница 58: ...O Data P2IO P2 Direction Register B9H 7 6 5 4 3 2 1 0 P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO R W R W R W R W R W R W R W R W Initial value 00H P2IO 7 0 P2 Data I O Direction 0 Input 1 Output...

Страница 59: ...0 I O Port 0 1 LCD_S15 Function 1 0 T4O PWM4O Function 1 1 reserved P2FSRH 5 4 P26 Function Select P2FSRH5 P2FSRH4 Description 0 0 I O Port 0 1 LCD_S14 Function 1 0 T5O PWM5O Function 1 1 reserved P2...

Страница 60: ...0 I O Port 0 1 LCD_S11 Function 1 0 reserved 1 1 TXD1 SDA1 MOSI1 Function P2FSRL 5 4 P22 Function Select P2FSRL5 P2FSRL4 Description 0 0 I O Port 0 1 LCD_S10 Function 1 0 reserved 1 1 RXD1 SCL1 MISO1...

Страница 61: ...Register 98H 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 R W R W R W R W R W R W R W R W Initial value 00H P3 7 0 I O Data P3IO P3 Direction Register C1H 7 6 5 4 3 2 1 0 P37IO P36IO P35IO P34IO P3...

Страница 62: ...O Port 0 1 LCD_C7 LCD_S20 Function 1 0 AN5 Function 1 1 LED_C7 Function P3FSRH 5 4 P36 Function Select P3FSRH5 P3FSRH4 Description 0 0 I O Port 0 1 LCD_C6 LCD_S21 Function 1 0 AN6 Function 1 1 LED_C6...

Страница 63: ...nction 1 1 LED_C3 Function P3FSRL 5 4 P32 Function Select P3FSRL5 P3FSRL4 Description 0 0 I O Port 0 1 LCD_C2 Function 1 0 AN10 Function 1 1 LED_C2 Function P3FSRL 3 2 P31 Function Select P3FSRL3 P3FS...

Страница 64: ...lue 00H P4 5 0 I O Data P4IO P4 Direction Register C9H 7 6 5 4 3 2 1 0 P45IO P44IO P43IO P42IO P41IO P40IO R W R W R W R W R W R W Initial value 00H P4IO 5 0 P4 Data I O Direction 0 Input 1 Output NOT...

Страница 65: ...4FSRH1 P4FSRH0 R W R W R W R W Initial value 00H P4FSRH 3 2 P45 Function Select P4FSRH3 P4FSRH2 Description 0 0 I O Port 0 1 LCD_S19 Function 1 0 T3O PWM3O Function 1 1 RXD2 MISO2 Function P4FSRH 1 0...

Страница 66: ...0 1 VLC3 Function 1 0 AN1 Function 1 1 XCK2 Function P4FSRL 5 4 P42 Function Select P4FSRL5 P4FSRL4 Description 0 0 I O Port EINT42 function possible when input 0 1 VLC2 Function 1 0 AN2 Function 1 1...

Страница 67: ...selection 6 7 2 Register description for P5 P5 P5 Data Register B0H 7 6 5 4 3 2 1 0 P53 P52 P51 P50 R W R W R W R W Initial value 00H P5 3 0 I O Data P5IO P5 Direction Register D1H 7 6 5 4 3 2 1 0 P5...

Страница 68: ...n 0 0 I O Port 0 1 reserved 1 0 reserved 1 1 BUZ0 Function P5FSR 5 4 P52 Function Select P5FSR5 P5FSR4 Description 0 0 I O Port 0 1 reserved 1 0 reserved 1 1 reserved P5FSR 3 2 P51 Function Select P5F...

Страница 69: ...received simultaneously Each interrupt source can be controlled by EA bit and each IEx bit Interrupt latency of 3 to 9 machine cycles in single interrupt system A non maskable interrupt is always enab...

Страница 70: ...igher priority interrupt first If two requests of different priority levels are received simultaneously the request of higher priority level is served prior to the lower one 0 Bit0 Interrupt Group 1 B...

Страница 71: ...pt source has enable disable bits External interrupt flag 0 register EIFLAG0 and external interrupt flag 1 register 1 EIFLAG1 indicate status of external interrupts EINT41 Pin EINT43 Pin EINT45 Pin EI...

Страница 72: ...Timer 0 overflow Timer 0 Timer 1 Timer 2 Timer 3 IP1 IP IE FLAG1 FLAG2 IE2 T0OVIFR T0IFR T1IFR T2IFR T3IFR FLAG40 FLAG41 FLAG42 FLAG43 FLAG44 FLAG45 FLAG46 FLAG47 EIPOL1 USI0 I2C USI0 Rx USI0 Tx IE1 I...

Страница 73: ...E1 2 9 Maskable 0043H USI0 Rx Interrupt INT9 IE1 3 10 Maskable 004BH USI0 Tx Interrupt INT10 IE1 4 11 Maskable 0053H External Interrupt 3 INT11 IE1 5 12 Maskable 005BH T0 Overflow Interrupt INT12 IE2...

Страница 74: ...ent instruction it needs 3 to 9 machine cycles to go to the interrupt service routine The interrupt service task is terminated by the interrupt return instruction RETI Once an interrupt request is gen...

Страница 75: ...ng of Interrupt Enable Register Case B in Figure 15 shows the effective time after controlling Interrupt Flag Registers Figure 15 Effective Timing of Interrupt Flag Register Interrupt Enable Register...

Страница 76: ...than INT1 is occurred Then INT0 is served immediately and then the remaining part of INT1 service routine is executed If the priority level of INT0 is same or lower than INT1 INT0 will be served afte...

Страница 77: ...controller 77 7 7 Interrupt enable accept timing Figure 17 Interrupt Response Timing Diagram Interrupt latched Interrupt goes active System Clock Max 4 Machine Cycle 4 Machine Cycle Interrupt Process...

Страница 78: ...nterrupt service routine address Figure 18 Correspondence between Vector Table Address and the Entry Address of ISR 0EH 2EH 0125H 0126H Basic Interval Timer Service Routine Address Basic Interval Time...

Страница 79: ...A96G150 User s manual 7 Interrupt controller 79 7 9 Saving restore general purpose registers Figure 19 Saving Restore Process Diagram and Sample Source...

Страница 80: ...errupt Return Instruction Interrupt sources are sampled at the last cycle of a command If an interrupt source is detected the lower 8 bit of interrupt vector INT_VEC is decided M8051W core makes inter...

Страница 81: ...set IP and IP1 are cleared to 00H If interrupts have the same priority level lower number interrupt is served first 7 11 3 External interrupt flag register EIFLAG0 and EIFLAG1 External Interrupt Flag...

Страница 82: ...rupt Enable Register 2 IE3 ABH R W 00H Interrupt Enable Register 3 IP B8H R W 00H Interrupt PriorityRegister IP1 F8H R W 00H Interrupt PriorityRegister 1 EIFLAG0 C0H R W 00H External Interrupt Flag 0...

Страница 83: ...its 0 All Interrupt disable 1 All Interrupt enable INT5E Enable or Disable External Interrupt 40 47 EINT40 EINT47 0 Disable 1 Enable INT4E Enable or Disable USI1 Tx Interrupt 0 Disable 1 Enable INT3E...

Страница 84: ...1E Enable or Disable External Interrupt 3 EINT3 0 Disable 1 Enable INT10E Enable or Disable USI0Tx Interrupt 0 Disable 1 Enable INT9E Enable or Disable USI0 Rx Interrupt 0 Disable 1 Enable INT8E Enabl...

Страница 85: ...or Disable Timer 4 5 Match Interrupt 0 Disable 1 Enable INT16E Enable or Disable Timer 3 Match Interrupt 0 Disable 1 Enable INT15E Enable or Disable Timer 2 Match Interrupt 0 Disable 1 Enable INT14E E...

Страница 86: ...INT20E Enable or Disable WT Interrupt 0 Disable 1 Enable INT19E Enable or Disable USART2 RX CRC Interrupt 0 Disable 1 Enable INT18E Enable or Disable ADC Interrupt 0 Disable 1 Enable IP Interrupt Pri...

Страница 87: ...7 POL46 POL45 POL44 R W R W R W R W R W R W R W R W Initial value 00H EIPOL0H 7 0 External interrupt EINT47 EINT46 EINT45 EINT44 polarity selection POLn 1 0 Description 0 0 No interrupt at any edge 0...

Страница 88: ...INT_ACK signal Writing 1 has no effect 0 T0 Interrupt no generation 1 T0 Interrupt generation EIFLAG1 3 0 When an External Interrupt EINT0 EINT3 is occurred the flag becomes 1 The flag is cleared by...

Страница 89: ...he external oscillator For this it is necessary to place external clock signal into the XIN1 XIN2 SXIN pin and open XOUT1 XOUT2 SXOUT pin Default system clock is 1MHz INT RC Oscillator To stabilize th...

Страница 90: ...pheral fx BIT WDT BIT overflow XIN2 XOUT2 Main OSC fXIN STOP Mode XCLKE STOP Mode HSIRCE 1 64 1 2 1 4 1 8 M U X LIRC OSC 128kHz WDTCK Stabilization Time Generation M U X BIT clock WDT clock SXIN SXOUT...

Страница 91: ...ster map Table 10 Clock Generator Register Map Name Address Direction Default Description SCCR 8AH R W 00H System and Clock Control Register OSCCR C8H R W 28H Oscillator Control Register XTFLSR 1038H...

Страница 92: ...ted XIN1 XOUT1 P07 P06 1 Selected XIN2 XOUT2 P50 P51 LSIRCE Control the Operation of the Low Frequency 128kHz internal RC Oscillator at Stop mode 0 Disable operation of LSIRC OSC 1 Enable operation of...

Страница 93: ...0 Using noise filter 1 Bypass noise filter MX_ISEL 1 0 Current selective option for MX TAL MX_ISEL1 MX_ISEL0 Description 0 0 HIGH 12M 0 1 MID HIGH 8 12M 1 0 MID LOW 4 8M 1 1 LOW 4M SUB_FIL_DIS SUB X...

Страница 94: ...ng Stop mode BIT gives a stable clock generation time As a timer BIT generates a timer interrupt 9 1 BIT block diagram In this section basic interval timer of A96G150 is described in a block diagram 3...

Страница 95: ...val Timer BIT 95 9 2 BIT register map Table 11 Basic Interval Timer Register Map Name Address Direction Default Description BITCNT 8CH R 00H Basic Interval Timer Counter Register BITCR 8BH R W 45H Bas...

Страница 96: ...comes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 BIT interrupt no generation 1 BIT interrupt generation BITCK 2 0 Select BIT clock source BITCK2 B...

Страница 97: ...DTCR 6 bit If WDTCR 5 is set to 1 the WDT counter value is cleared and counts up After 1 machine cycle this bit is cleared to 0 automatically The WDT consists of an 8 bit binary counter and a watchdog...

Страница 98: ...IT Overflow or BIT Overflow 8 WDTCNT Watchdog Timer Counter Register WDTDR 8EH 8EH comparator WDTCR Watchdog Timer Data Register Clear WDTCL WDTRSON WDTIFR Clear WDTEN INT_ACK WDTIF To Reset Circuit B...

Страница 99: ...10 3 Register map Table 12 Watchdog Timer Register Map Name Address Direction Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR...

Страница 100: ...Value 1 NOTE Do not write 0 in the WDTDR register WDTCR Watch Dog Timer Control Register 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL WDTCK WDTIFR R W R W R W R W R W Initial value 00H WDTEN Control WDT O...

Страница 101: ...ch timer counter circuits may be composed of 21 bit counter which contains low 14 bit with binary counter and high 7 bit counter in order to increase resolution In WTDR it can control WT clear and set...

Страница 102: ...nual 102 11 2 Register map Table 13 Watch Timer Register Map Name Address Direction Default Description WTCNT 89H R 00H Watch Timer Counter Register WTDR 89H W 7FH Watch Timer Data Register WTCR 96H R...

Страница 103: ...ch Timer Data Register Write Case 89H 7 6 5 4 3 2 1 0 WTCL WTDR6 WTDR5 WTDR4 WTDR3 WTDR2 WTDR1 WTDR0 R W W W W W W W W Initial value 7FH WTCL Clear WT Counter 0 Free Run 1 Clear WT Counter auto clear...

Страница 104: ...this bit or automatically clear by INT_ACK signal Writing 1 has no effect 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval WTIN1 WTIN0 Description 0 0 fWCK...

Страница 105: ...egister T0CDR by EINT1 In timer counter mode whenever counter value is equal to T0DR T0O port toggles In addition timer 0 outputs PWM waveform through PWM0O port in the PWM mode Table 14 Timer 0 Opera...

Страница 106: ...e r fx M U X fx 2 T0CNT 8Bit EC0 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T0CK 2 0 T0EN 8 bit Timer 0 Counter T0DR 8Bit Comparator T0IFR T0O PWM0O 8 bit Timer 0 Data Register INT_ACK Clear Match signa...

Страница 107: ...imer 0 occurs In PWM mode the match signal does not clear the counter Instead it runs continuously overflowing at FFH Then the counter continues incrementing from 00H The timer 0 overflow interrupt is...

Страница 108: ...0PWM 00H 01H 02H 4AH FFH FEH 00H T0 Match Interrupt T0 Overflow Interrupt T0DR 1 T0DR 4AH Timer 0 clock Set T0EN T0PWM T0 Match Interrupt 2 T0DR 00H T0PWM T0 Match Interrupt 3 T0DR FFH PWM Mode T0MS 0...

Страница 109: ...0 output T0O waveform is not available According to EIPOL1 registers setting the external interrupt EINT1 function is chosen Of course the EINT1 pin must be set to an input port T0CDR and T0DR are in...

Страница 110: ...Value Interrupt Request FLAG1 Ext EINT1 PIN Interrupt Interval Period Figure 31 Input Capture Mode Operation for Timer 0 T0CNT Interrupt Request FLAG1 Ext EINT1 PIN Interrupt Interval Period FFH 01H...

Страница 111: ...r INT_ACK Clear Clear Match MUX T0CDR 8Bit Clear T0OVIFR To interrupt block Clear EINT1 EIPOL1 3 2 FLAG1 EIFLAG1 1 INT_ACK Clear To interrupt block 2 T0MS 1 0 2 T0MS 1 0 2 Match signal T0CC Figure 33...

Страница 112: ...nitial value 00H T0CNT 7 0 T0 Counter T0DR Timer 0 Data Register B4H 7 6 5 4 3 2 1 0 T0DR7 T0DR6 T0DR5 T0DR4 T0DR3 T0DR2 T0DR1 T0DR0 R W R W R W R W R W R W R W R W Initial value FFH T0DR 7 0 T0 Data...

Страница 113: ...nter mode 0 1 PWM mode 1 x Capture mode T0CK 2 0 Select Timer 0 clock source fx is a system clock frequency T0CK2 T0CK1 T0CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1 fx 32 1 0 0 fx 128 1 0...

Страница 114: ...ddition Timer 1 outputs PWM waveform through PWM1Oport in the PPG mode Table 16 TIMER 1 Operating Modes T1EN P0FSRL 5 4 T1MS 1 0 T1CK 2 0 Timer 1 1 10 00 XXX 16 Bit Timer Counter Mode 1 00 01 XXX 16 B...

Страница 115: ...ear Edge Detector T1ECE EC1 Comparator 16 bit A Data Register T1ADRH T1ADRL T1IFR INT_ACK Clear To interrupt block A Match Buffer Register A A Match T1CC Reload Pulse Generator T1O R T1EN 3 T1CK 2 0 2...

Страница 116: ...RL According to EIPOL1 registers setting the external interrupt EINT2 function is selected EINT2 pin must be set as an input port A Match T1CC T1EN P r e s c a l e r fx M U X fx 2 fx 4 fx 64 fx 512 fx...

Страница 117: ...Value Interrupt Request FLAG2 Ext EINT2 PIN Interrupt Interval Period Figure 37 16 bit Capture Mode Operation Example T1CNTH L Interrupt Request FLAG2 Ext EINT2 PIN Interrupt Interval Period FFFFH 01H...

Страница 118: ...x 4 fx 64 fx 512 fx 2048 fx 8 fx 1 Comparator 16 bit Counter T1CNTH T1CNTL 16 bit B Data Register T1BDRH T1BDRL Clear B Match Edge Detector T1ECE EC1 Buffer Register B Comparator 16 bit A Data Registe...

Страница 119: ...A Match 1 T1BDRH L 5 T1ADRH L PWM1O A Match 2 T1BDRH L T1ADRH L PWM1O A Match 3 T1BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 1 clock Counter T1ADRH L T1 Interrupt PWM1O B Match One shot Mode T1M...

Страница 120: ...h Buffer Register A Reload Pulse Generator T1O PWM1O R EINT2 T1CNTR T1EN 3 T1CK 2 0 Clear EIPOL1 5 4 FLAG2 EIFLAG1 2 INT_ACK Clear To interrupt block 2 2 T1MS 1 0 2 Edge Detector T1ECE EC1 To Timer 2...

Страница 121: ...T1ADRL2 T1ADRL1 T1ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T1ADRL 7 0 T1 A Data Low Byte NOTE Do not write 0000H in the T1ADRH T1ADRL register when PPG mode T1BDRH Timer 1 B Data High R...

Страница 122: ...disable 1 Timer 1 enable Counter clear and start T1MS 1 0 Control Timer 1 Operation Mode T1MS1 T1MS0 Description 0 0 Timer counter mode T1O toggle at A match 0 1 Capture mode The A match interrupt can...

Страница 123: ...lock EC1 T1IFR When T1 Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 T1 Interrupt no generation 1 T1 Interrupt gene...

Страница 124: ...scaler output and T1 A Match timer 1 A match signal The clock source is selected by a clock selection logic controlled by clock selection bits T2CK 2 0 TIMER 2 clock source fx 1 fx 2 fx 4 fx 8 fx 32 f...

Страница 125: ...nterrupt of Timer 2 occurs The T2CNTH T2CNTL values are automatically cleared by the match signal It can be cleared by software T2CC too T2MS 1 0 T2POL A Match T2CC T2EN P r e s c a l e r fx M U X fx...

Страница 126: ...12 Timer 0 1 2 3 4 5 A96G150 User s manual 126 Figure 43 16 bit Timer Counter Mode Operation Example...

Страница 127: ...utput T2O waveform is not available According to EIPOL1 registers setting the external interrupt EINT3 function is selected EINT3 pin must be set as an input port A Match T2CC T2EN P r e s c a l e r f...

Страница 128: ...Value Interrupt Request FLAG3 Ext EINT3 PIN Interrupt Interval Period Figure 45 16 bit Capture Mode Operation Example T2CNTH L Interrupt Request FLAG3 Ext EINT3 PIN Interrupt Interval Period FFFFH 01H...

Страница 129: ...8 fx 1 Comparator 16 bit Counter T2CNTH T2CNTL 16 bit B Data Register T2BDRH T2BDRL Clear B Match T1 A Match Buffer Register B Comparator 16 bit A Data Register T2ADRH T2ADRL T2IFR INT_ACK Clear To i...

Страница 130: ...A Match 1 T2BDRH L 5 T2ADRH L PWM2O A Match 2 T2BDRH L T2ADRH L PWM2O A Match 3 T2BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 2 clock Counter T2ADRH L T2 Interrupt PWM2O B Match One shot Mode T2M...

Страница 131: ...oad Pulse Generator T2O PWM2O R EINT3 T2CNTR T2EN 3 T2CK 2 0 Clear EIPOL1 7 6 FLAG3 EIFLAG1 3 INT_ACK Clear To interrupt block 2 2 T2MS 1 0 2 T1 A Match A Match T2CC T2EN A Match T2CC T2EN NOTE T1 A M...

Страница 132: ...3 T2ADRL2 T2ADRL1 T2ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T2ADRL 7 0 T2 A Data Low Byte NOTE Do not write 0000H in the T2ADRH T2ADRL register when PPG mode T2BDRH Timer 2 B Data High...

Страница 133: ...olLow Register C2H 7 6 5 4 3 2 1 0 T2CK2 T2CK1 T2CK0 T2IFR T2POL T2CNTR R W R W R W R W R W R W Initial value 00H T2CK 2 0 Select Timer 2 clock source fx is main system clock frequency T2CK2 T2CK1 T2C...

Страница 134: ...ck source EC3 The clock source is selected by a clock selection logic controlled by clock selection bits T3CK 2 0 TIMER 3 clock source fx 1 fx 2 fx 4 fx 8 fx 64 fx 512 fx 2048 and EC3 In capture mode...

Страница 135: ...d by the match signal It can be cleared by software T3CC too External clock EC3 counts up the timer at the rising edge If the EC3 is selected as a clock source by T3CK 2 0 EC3 port should be set as an...

Страница 136: ...12 Timer 0 1 2 3 4 5 A96G150 User s manual 136 Figure 51 16 bit Timer Counter Mode Operation Example...

Страница 137: ...loaded into T3BDRH T3BDRL According to EIPOL0L registers setting the external interrupt EINT43 function is selected EINT43 pin must be set as an input port A Match T3CC T3EN P r e s c a l e r fx M U...

Страница 138: ...lue Interrupt Request FLAG43 Ext EINT43 PIN Interrupt Interval Period Figure 53 16 bit Capture Mode Operation Example T3CNTH L Interrupt Request FLAG43 Ext EINT43 PIN Interrupt Interval Period FFFFH 0...

Страница 139: ...X fx 2 fx 4 fx 64 fx 512 fx 2048 fx 8 fx 1 Comparator 16 bit Counter T3CNTH T3CNTL 16 bit B Data Register T3BDRH T3BDRL Clear B Match Edge Detector T3ECE EC3 Buffer Register B Comparator 16 bit A Data...

Страница 140: ...A Match 1 T3BDRH L 5 T3ADRH L PWM3O A Match 2 T3BDRH L T3ADRH L PWM3O A Match 3 T3BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 3 clock Counter T3ADRH L T3 Interrupt PWM3O B Match One shot Mode T3M...

Страница 141: ...Register A Reload Pulse Generator T3O R EINT43 T3CNTR T3EN Clear EIPOL0L 7 6 FLAG43 EIFLAG0 3 INT_ACK Clear To interrupt block 2 2 T3MS 1 0 2 Edge Detector T3ECE EC3 To Timer 4 block A Match T3CC T3E...

Страница 142: ...T3ADRL2 T3ADRL1 T3ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T3ADRL 7 0 T3 A Data Low Byte NOTE Do not write 0000H in the T3ADRH T3ADRL register when PPG mode T3BDRH Timer 3 B Data High R...

Страница 143: ...disable 1 Timer 3 enable Counter clear and start T3MS 1 0 Control Timer 3 Operation Mode T3MS1 T3MS0 Description 0 0 Timer counter mode T3O toggle at A match 0 1 Capture mode The A match interrupt ca...

Страница 144: ...clock EC3 T3IFR When T3 Interrupt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 T3 Interrupt no generation 1 T3 Interrupt ge...

Страница 145: ...er output and T3 A Match timer 3 A match signal The clock source is selected by a clock selection logic controlled by clock selection bits T4CK 2 0 TIMER 4 clock source fx 1 fx 2 fx4 fx 8 fx 32 fx 128...

Страница 146: ...rrupt of Timer 4 occurs The T4CNTH T4CNTL values are automatically cleared by the match signal It can be cleared by software T4CC too T4MS 1 0 T4POL A Match T4CC T4EN P r e s c a l e r fx M U X fx 2 f...

Страница 147: ...A96G150 User s manual 12 Timer 0 1 2 3 4 5 147 Figure 59 16 bit Timer Counter Mode Operation Example...

Страница 148: ...tput T4O waveform is not available According to EIPOL0L registers setting the external interrupt EINT44 function is selected EINT44 pin must be set as an input port A Match T4CC T4EN P r e s c a l e r...

Страница 149: ...lue Interrupt Request FLAG44 Ext EINT44 PIN Interrupt Interval Period Figure 61 16 bit Capture Mode Operation Example T4CNTH L Interrupt Request FLAG44 Ext EINT44 PIN Interrupt Interval Period FFFFH 0...

Страница 150: ...8 fx 1 Comparator 16 bit Counter T4CNTH T4CNTL 16 bit B Data Register T4BDRH T4BDRL Clear B Match T3 A Match Buffer Register B Comparator 16 bit A Data Register T4ADRH T4ADRL T4IFR S W Clear To inter...

Страница 151: ...A Match 1 T4BDRH L 5 T4ADRH L PWM4O A Match 2 T4BDRH L T4ADRH L PWM4O A Match 3 T4BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 4 clock Counter T4ADRH L T4 Interrupt PWM4O B Match One shot Mode T4M...

Страница 152: ...Generator T4O R EINT44 T4CNTR T4EN 3 T4CK 2 0 Clear EIPOL0H 1 0 FLAG44 EIFLAG0 4 INT_ACK Clear To interrupt block 2 2 T4MS 1 0 2 T3 A Match A Match T4CC T4EN A Match T4CC T4EN PWM4O NOTE T3 A Match i...

Страница 153: ...3 T4ADRL2 T4ADRL1 T4ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T4ADRL 7 0 T4 A Data Low Byte NOTE Do not write 0000H in the T4ADRH T4ADRL register when PPG mode T4BDRH Timer 4 B Data High...

Страница 154: ...CRL Timer 4 Control Low Register 1009H 7 6 5 4 3 2 1 0 T4CK2 T4CK1 T4CK0 T4IFR T4POL T4CNTR R W R W R W R W R W R W Initial value 00H T4CK 2 0 Select Timer 4 clock source fx is main system clock frequ...

Страница 155: ...selected from prescaler output The clock source is selected by a clock selection logic controlled by clock selection bits T5CK 2 0 TIMER 5 clock source fx 1 fx 2 fx 4 fx 8 fx 32 fx 128 fx 512 and HSIR...

Страница 156: ...mer 5 a match signal is generated and the interrupt of Timer 5 occurs The T5CNTH T5CNTL values are automatically cleared by the match signal It can be cleared by software T5CC too T5MS 1 0 T5POL A Mat...

Страница 157: ...A96G150 User s manual 12 Timer 0 1 2 3 4 5 157 Figure 67 16 bit Timer Counter Mode Operation Example...

Страница 158: ...L In the timer 5 capture mode timer 5 output T5O waveform is not available According to EIPOL0H registers setting the external interrupt EINT45 function is selected EINT45 pin must be set as an input...

Страница 159: ...lue Interrupt Request FLAG45 Ext EINT45 PIN Interrupt Interval Period Figure 69 16 bit Capture Mode Operation Example T5CNTH L Interrupt Request FLAG45 Ext EINT45 PIN Interrupt Interval Period FFFFH 0...

Страница 160: ...x M U X fx 2 fx 4 fx 32 fx 128 fx 512 fx 8 fx 1 Comparator 16 bit Counter T5CNTH T5CNTL 16 bit B Data Register T5BDRH T5BDRL Clear B Match HIRC Buffer Register B Comparator 16 bit A Data Register T5AD...

Страница 161: ...A Match 1 T5BDRH L 5 T5ADRH L PWM5O A Match 2 T5BDRH L T5ADRH L PWM5O A Match 3 T5BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 5 clock Counter T5ADRH L T5 Interrupt PWM5O B Match One shot Mode T5M...

Страница 162: ...k A Match Buffer Register A Reload Pulse Generator T5O R EINT45 T5CNTR T5EN 3 T5CK 2 0 Clear EIPOL0H 3 2 FLAG45 EIFLAG0 5 INT_ACK Clear To interrupt block 2 2 T5MS 1 0 2 HIRC A Match T5CC T5EN A Match...

Страница 163: ...3 T5ADRL2 T5ADRL1 T5ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T5ADRL 7 0 T5 A Data Low Byte NOTE Do not write 0000H in the T5ADRH T5ADRL register when PPG mode T5BDRH Timer 5 B Data High...

Страница 164: ...Timer 5 Control Low Register 1011H 7 6 5 4 3 2 1 0 T5CK2 T5CK1 T5CK0 T5IFR T5POL T5CNTR R W R W R W R W R W R W Initial value 00H T5CK 2 0 Select Timer 5 clock source fx is main system clock frequency...

Страница 165: ...ided by prescaler Table 26 Buzzer Frequency at 8MHz BUZDR 7 0 Buzzer frequency KHz BUZCR 2 1 00 BUZCR 2 1 01 BUZCR 2 1 10 BUZCR 2 1 11 0000_0000 125KHz 62 5KHz 31 25KHz 15 625KHz 0000_0001 62 5KHz 31...

Страница 166: ...driver A96G150 User s manual 166 13 2 Register map Table 27 Buzzer Driver Register Map Name Address Direction Default Description BUZDR 8FH R W FFH Buzzer Data Register BUZCR 97H R W 00H Buzzer Contro...

Страница 167: ...FFH BUZDR 7 0 This bits control the Buzzer frequency Its resolution is 00H FFH BUZCR Buzzer Control Register 97H 7 6 5 4 3 2 1 0 BUCK1 BUCK0 BUZEN R W R W R W Initial value 00H BUCK 1 0 Buzzer Driver...

Страница 168: ...ers ADCDRH and ADCDRL contain the result of A D conversion When the conversion is completed the result is loaded into ADCDRH and ADCDRL A D conversion status bit AFLAG is set to 1 and A D interrupt is...

Страница 169: ...3 0 Select one input pin of the assigned pins ADCLK Input Pins M U X AN0 Reference Voltage AVREF AVSS AN1 AN2 AN13 ADCIFR AFLAG INT_ACK Clear Clear To interrupt block MUX VDD Start M U X T3 A match s...

Страница 170: ...3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCD...

Страница 171: ...A96G150 User s manual 14 12 bit ADC 171 Figure 79 ADC Operation Flow Sequence...

Страница 172: ...ADC Register Map Name Address Direction Default Description ADCDRH 9FH R xxH A D Converter Data High Register ADCDRL 9EH R xxH A D Converter Data Low Register ADCCRH 9DH R W 01H A D Converter Control...

Страница 173: ...DL8 R R R R R R R R Initial value xxH ADDM 11 4 MSB align A D Converter High Data 8 bit ADDL 11 8 LSB align A D Converter High Data 4 bit ADCDRL A D Converter Data Low Register 9EH 7 6 5 4 3 2 1 0 ADD...

Страница 174: ...ation IREF Select internal voltage reference Keep always 0 0 External input signal source select AN0 AN1 AN14 1 Reserved TRIG 2 0 A D Trigger Signal Selection TRIG2 TRIG1 TRIG0 Description 0 0 0 ADST...

Страница 175: ...Conversion Start and auto clear REFSEL A D Converter Reference Selection 0 Internal Reference VDD 1 External Reference AVREF AFLAG A D Converter Operation State This bit is cleared to 0 when the STBY...

Страница 176: ...control registers 1 2 3 4 USI status registers 1 2 USI baud rate generation register USI data register USI SDA hold time register USI SCL high period register USI SCL low period register and USI slav...

Страница 177: ...mprises clock generator transmitter and receiver Clock generation logic consists of synchronization logic for external clock input used by synchronizing or SPI slave operation and the baud rate genera...

Страница 178: ...or Transmit Shift Register TXSR USInDR USInTX8 Tx USInP 1 0 M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn RXCIEn WAKEIEn WAKEn At Stop mode To interrupt block...

Страница 179: ...in USInCR1 register selects one from asynchronous operation and synchronous operation Asynchronous double speed mode is controlled by the DBLSn bit in the USInCR2 register The MASTERn bit in USInCR3...

Страница 180: ...External clock input from the SCKn pin is sampled by a synchronization logic to remove meta stability The output from the synchronization logic must be passed through an edge detector before it is us...

Страница 181: ...ge of SCKn clock respectively For example if data input on RXDn MISOn in SPI mode pin is sampled on the rising edge of SCKn clock data output on TXDn MOSIn in SPI mode pin is altered on the falling ed...

Страница 182: ...d the stop bit A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set to a...

Страница 183: ...set up once before doing any transmission In synchronous operation mode the SCKn pin is used as transmission clock so it should be selected to do SCKn function by P1FSRH 7 6 P1FSRL 5 4 and P2FSRH 1 0...

Страница 184: ...is set The transmit complete TXCn flag bit is set when the entire frame in the transmit shift register has been shifted out and there is no more data in the transmit buffer The TXCn flag is automatica...

Страница 185: ...ents of the shift register are to be moved into the receive buffer The receive buffer is read by reading the USInDR register If 9 bit characters are used USInS 2 0 111 the ninth bit is stored in the U...

Страница 186: ...If parity check function is not enabled USInPM1 0 the PE bit is always read 0 15 9 3 USIn UART parity checker If parity bit is enabled USInPM1 1 the Parity Checker calculates the parity of the data b...

Страница 187: ...mode to decide if a valid start bit is received If more than 2 samples have logical low level it is considered that a valid start bit is detected and the internally generated clock is synchronized to...

Страница 188: ...ity Bit USIn The process for detecting stop bit is same as clock and data recovery process That is if 2 or more samples of 3 center values have high level correct stop bit is detected else a frame err...

Страница 189: ...l four SPIn modes of operation mode 0 1 2 and 3 Selectable LSB first or MSB first data transfer Double buffered transmit and receive Programmable transmit bit rate When SPI mode is enabled USInMS 1 0...

Страница 190: ...verter in series with the clock CPHAn chooses between two different clock phase relationships between the clock and data Note that CPHAn and CPOLn bits in USInCR1 register have different meanings acco...

Страница 191: ...and MOSIn inputs respectively At the second SCKn edge the USIn shifts the second data bit value out to the MOSIn and MISOn outputs of the master and slave respectively Unlike the case of CPHAn 1 when...

Страница 192: ...lue out to the MOSIn and MISOn output of the master and slave respectively When CPHAn 1 the slave s SSn input is not required to go to its inactive high level between transfers Because the SPI logic r...

Страница 193: ...TXSR USInDR Tx I N T E R N A L B U S L I N E M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn Baud Rate Generator USInBD TXEn SCLK fx System clock MISOn MOSIn M U...

Страница 194: ...The I2C mode uses 2 bus lines serial data line SDAn and serial clock line SCLn to exchange data Because both SDAn and SCLn lines are open drain output each line needs pull up resistor The features ar...

Страница 195: ...d of the clock SCLn The HIGH or LOW state of the data line can only change when the clock signal on the SCLn line is LOW The exceptions are START S repeated START Sr and STOP P condition where data li...

Страница 196: ...h defines a START S condition A low to high transition on the SDAn line while SCLn is high defines a STOP P condition START and STOP conditions are always generated by the master The bus is considered...

Страница 197: ...other complete byte of data until it has performed some other function it can hold the clock line SCLn LOW to force the master into a wait state Data transfer then continues when the slave is ready fo...

Страница 198: ...t be left HIGH by the slave And also when a slave addressed by a master is unable to receive more data bits the slave receiver must release the SDAn line Data Packet The master can then generate eithe...

Страница 199: ...with the shortest clock HIGH period A master may start a transfer only if the bus is free Two or more masters may generate a START condition Arbitration takes place on the SDAn line while the SCLn li...

Страница 200: ...ovides main clock to the peripheral 2 Load SLAn W into the USInDR where SLAn is address of slave device and W is transfer direction from the viewpoint of the master For master transmitter W is 0 Note...

Страница 201: ...STARTCn bit in USInCR4 After doing one of the actions above write any arbitrary to USInST2 to release SCLn line For the case 1 move to step 7 For the case 2 move to step 9 to handle STOP interrupt For...

Страница 202: ...f the master For master receiver R is 1 Note that USInDR is used for both address and data 3 Configure baud rate by writing desired value to both USInSCLR and USInSCHR for the Low and High period of S...

Страница 203: ...due to no ACK signal from slave In this case load SLAn R W into the USInDR and set STARTCn bit in USInCR4 After doing one of the actions above write arbitrary value to USInST2 to release SCLn line Fo...

Страница 204: ...number of SCLK coming from USInSDHR When the hold time of SDAn is longer than the period of SCLK I2C slave cannot transmit serial data properly 2 Enable I2C by setting USInMS 1 0 bits in USInCR1 IICnI...

Страница 205: ...ulated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USInSDHR When the hold time of SDAn is longer than the period of SCLK I2C slave cannot transmit serial data properl...

Страница 206: ...ns above write arbitrary value to USInST2 to release SCLn line For the case 1 move to step 7 to terminate communication For the case 2 move to step 5 In either case a repeated START condition can be d...

Страница 207: ...ler USInDR Tx Slave Address Register USInSAR General Call And Address Detector USInGCE STOP START Condition Generator STOPCn STARTCn ACK Signal Generator ACKnEN RXACKn GCALLn TENDn STOPDn SSELn MLOSTn...

Страница 208: ...er 2 USI0CR3 DBH R W 00H USI0 Control Register 3 USI0CR4 DCH R W 00H USI0 Control Register 4 USI0ST1 E1H R W 80H USI0 Status Register 1 USI0ST2 E2H R 00H USI0 Status Register 2 USI1BD F3H R W FFH USI1...

Страница 209: ...0 The USIn transmit buffer and receive buffer share the same I O address with this DATA register The transmit data buffer is the destination for data written to the USInDR register Reading the USInDR...

Страница 210: ...1 7 6 5 4 3 2 1 0 USInSCLR7 USInSCLR6 USInSCLR5 USInSCLR4 USInSCLR3 USInSCLR2 USInSCLR1 USInSCLR0 R W R W R W R W R W R W R W R W Initial value 3FH USInSCLR 7 0 This register defines the high period...

Страница 211: ...ts the length of data bits in frame USInS2 USInS1 USInS0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit ORDn This bit in the same...

Страница 212: ...nterrupt WAKEIEn Interrupt enable bit for asynchronous wake in STOP mode When device is in stop mode if RXDn goes to low level an interrupt can be requested to wake up system only UART mode At that ti...

Страница 213: ...utput 0 ACK is free running while UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring USInSSEN This bit controls the SSn pin operation only SPI mode 0 Disable...

Страница 214: ...Enable bit for I2C mode 0 Interrupt from I2C is inhibited use polling 1 Enable interrupt for I2C ACKnEN Controls ACK signal Generation at ninth SCLn period 0 No ACK signal is generated SDAn 1 1 ACK s...

Страница 215: ...sed to generate an RXCn interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKEn This flag is set when the RXDn pin is detected low while the...

Страница 216: ...his bit is set when a STOP condition is detected 0 No STOP condition is detected 1 STOP condition is detected SSELnNOTE This bit is set when I2C is addressed by other master 0 I2C is not selected as a...

Страница 217: ...r USI0BD USI1BD Error 2400 25 0 2 47 0 0 51 0 2 4800 12 0 2 23 0 0 25 0 2 9600 6 7 0 11 0 0 12 0 2 14 4k 3 8 5 7 0 0 8 3 5 19 2k 2 8 5 5 0 0 6 7 0 28 8k 1 8 5 3 0 0 3 8 5 38 4k 1 18 6 2 0 0 2 8 5 57 6...

Страница 218: ...cillator Frequencies Baud rate bps fx 8 00MHz fx 11 0592MHz USI0BD USI1BD Error USI0BD USI1BD Error 2400 207 0 2 4800 103 0 2 143 0 0 9600 51 0 2 71 0 0 14 4k 34 0 8 47 0 0 19 2k 25 0 2 35 0 0 28 8k 1...

Страница 219: ...and RX Complete Double Speed Asynchronous Communication Mode USART2 has three main parts such as a Clock Generator Transmitter and Receiver Clock Generation logic consists of a synchronization logic f...

Страница 220: ...rator UDATA Tx SS2 SS Control RXC TXC UPM1 UPM0 USIZE2 USIZE1 USIZE0 UCPOL UCTRL1 ADDRESS CBH INITIAL VALUE 0000_0000B UDRIE TXCIE RXCIE TXE RXE U2X UCTRL2 ADDRESS CCH INITIAL VALUE 0000_0000B LOOPS S...

Страница 221: ...olled by the U2X bit in the UCTRL2 register The MASTER bit in UCTRL2 register controls whether the clock source is internal Master mode output port or external Slave mode input port The XCK pin is onl...

Страница 222: ...ion logic to remove meta stability The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver This process introduces a two...

Страница 223: ...s that data input on RXD2 MISO2 in SPI mode pin is sampled at the opposite XCK clock edge at the edge in the data output on TXD2 MOSI2 in SPI mode pin is changed UCPOL bit in UCTRL1 register selects w...

Страница 224: ...the stop bits A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set to an...

Страница 225: ...l the data bits If odd parity is used the result of the exclusive or is inverted The parity bit is located between St bits and first stop bit of a serial frame Peven Dn 1 D3 D2 D1 D0 0 Podd Dn 1 D3 D2...

Страница 226: ...synchronous operation mode USIZE 2 0 7 the ninth bit must be written to the TX8 bit in UCTRL3 register before loading a transmit buffer UDATA register 16 7 2 Transmitter flag and interrupt The USART2...

Страница 227: ...M 1 1 transmitter control logic inserts the parity bit between bits and the first stop bit of the sending frame 16 7 4 Disabling transmitter Disabling the Transmitter by clearing TXE bit will not beco...

Страница 228: ...e to be moved into the receive buffer The receive buffer is read by reading the UDATA register If 9 bit characters are used USIZE 2 0 7 the ninth bit is stored in RX8 bit field in the UCTRL3 register...

Страница 229: ...ways read 0 NOTE The error flags related to the receive operation are not used when USART2 is in SPI mode 16 8 3 Parity checker If Parity bit is enabled UPM 1 1 Parity Checker calculates parity of dat...

Страница 230: ...rmal mode and the samples 4 5 and 6 for Double Speed mode to decide if a valid start bit is received If more than 2 samples have logical low level it is considered that a valid start bit is detected a...

Страница 231: ...nd waiting to find start bit Figure 102 Sampling of Data and Parity Bit A process for detecting stop bit is similar to the clock and data recovery process That is if 2 or more samples of 3 center valu...

Страница 232: ...r compatibility to other SPI devices 16 9 1 SPI clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers the USART2 has a clock polarity bi...

Страница 233: ...uts respectively At the second XCK edge the USART2 shifts the second data bit value out to the MOSI and MISO2 outputs of the master and slave respectively Unlike the case of UCPHA 1 when UCPHA 0 the s...

Страница 234: ...he MOSI2 and MISO2 output of the master and slave respectively When UCPHA 1 the slave s SS input is not required to go to its inactive high level between transfers Because an SPI logic reuses the USAR...

Страница 235: ...Calculated UBAUD 1000000 Target Baud rate 1 7 68 Error rate 0 68 UBAUD 8 Real baud rate at sysclk 16Mhz 111 111 bps 1 bit time 9us Maximum count time 9us 65536 16bit count 589 8ms USART RX Start bit D...

Страница 236: ...Register UCTRL3 CDH R W 00H USART2 Control 3 Register UCTRL4 1018H R W 00H USART2 Control 4 Register USTAT CFH R 80H USART2 Status Register UBAUD FCH R W FFH USART2 Baud Rate Generation Register UDAT...

Страница 237: ...erved 1 1 0 Reserved 1 1 1 9 bit UDORD This bit is in the same bit position with USIZE1 In SPI mode when set to one the MSB of the data byte is transmitted first When set to zero the LSB of the data b...

Страница 238: ...rrupt enable bit for Asynchronous Wake in STOP mode When device is in stop mode if RXD2 goes to LOW level an interrupt can be requested to wake up system 0 Interrupt from Wake is inhibited 1 When WAKE...

Страница 239: ...hile USART is enabled in synchronous master mode 1 XCK is active while any frame is on transferring SPISS Controls the functionality of SS2 pin in master SPI mode 0 SS2 pin is normal GPIO or other pri...

Страница 240: ...ble 1 Enable RTO_FLAG This bit is set when RTO count overflows This flag can generate an RTO interrupt Writing 0 to this bit position will clear RTO_FLAG 0 RTO count dose not overflow 1 RTO count over...

Страница 241: ...s no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKE This flag is set when the RX pin is detected low while the CPU is in stop mode This flag can be used to g...

Страница 242: ...Receive Buffer Write this register only when the UDRE flag is set In SPI or synchronous master mode write this register even if TX is not enabled to generate clock XCK FPCR USART Floating Point Regist...

Страница 243: ...5 4 3 2 1 0 RTOCH7 RTOCH6 RTOCH5 RTOCH4 RTOCH3 RTOCH2 RTOCH1 RTOCH0 R W R W R W R W R W R W R W R W Initial value 00H RTOCL Receiver Time Out Counter Low Register 101BH 7 6 5 4 3 2 1 0 RTOCL7 RTOCL6...

Страница 244: ...0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4K 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2K 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8K 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31 0 0...

Страница 245: ...or example If you want to use the 57600 baud rate fXIN 16MHz integer count value must be 16 36 value BAUD 1 16000000 16 57600 17 36 Here the accurate BAUD value is 16 36 To achieve the 0 error of baud...

Страница 246: ...CLK 1 0 determines the frequency of COM signal scanning of each segment output A RESET clears the LCD control register LCD_CR and LCD_BCCR values to logic 0 The LCD display can continue operating duri...

Страница 247: ...ts of the display external data area with a program Figure 108 shows the correspondence between the display external data area and the COM SEG pins The LCD is turned on when the display data is 1 and...

Страница 248: ...1 COM0 SEG4 SEG2 SEG3 COM2 1 Frame VDD VSS 0 1 COM1 SEG3 COM0 SEG2 COM0 VLC2 VLC0 VLC1 SEG2 VLC2 VLC0 VLC1 VSS VLC2 2 0 1 2 VSS VLC2 VLC0 VLC1 VSS COM2 VLC2 VLC0 VLC1 VSS VLC2 VLC0 VLC1 VSS VLC2 VLC0...

Страница 249: ...3 COM3 COM2 1 Frame VDD VSS 0 1 COM1 SEG4 COM0 SEG3 COM0 VLC2 VLC0 VLC1 SEG3 VLC2 VLC0 VLC1 VSS VLC2 2 VSS VLC2 VLC0 VLC1 VSS COM2 VLC2 VLC0 VLC1 VSS VLC2 VLC0 VLC1 VSS VLC2 VLC0 VLC1 VSS VLC0 VLC1 3...

Страница 250: ...9 S E G 1 0 1 Frame VDD VSS 0 COM1 SEG7 COM0 SEG6 COM0 VLC2 VLC0 VLC1 SEG6 VSS COM2 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC...

Страница 251: ...LCD 1 3 BIAS R Contrast Controller LCTEN DISP Contrast Controller LCTEN DISP Contrast Controller R NOTES 1 When 1 2 bias are selected the VLC1 VLC2 and VLC3 are internally connected 2 When 1 3 bias ar...

Страница 252: ...2 VLC3 R R R R NOTES 1 When the external resistor bias is selected the internal resistors for bias are disconnected 2 When the external resistor bias is selected the dividing resistors should be conne...

Страница 253: ...timing Bias Mode A Bias Mode B Bias Mode A Bias Mode B NOTE Refer to the below when the LCD automatic bias is on Bias Mode A Always RLCD1 10k Bias Mode B A LCD bias dividing resistor which is selected...

Страница 254: ...DATA Register Display Data Select Controller and Display Data Buffer Register Segment Driver Common Driver LCD Voltage Bias LCD_BCCR LCD_CR Timing Controller LCLK M U X fx SUB OSC WDTRC 2 LCDCLKSEL of...

Страница 255: ...D Driver Control Register LCDBCCRH 1049H R W 00H LCD Automatic Bias and Contrast Control High Register LCDBCCRL 104AH R W 00H LCD Automatic Bias and Contrast Control Low Register LCDBSSRH 104BH R W 00...

Страница 256: ...50 k 1 2 1 3 1 4 bias 1 1 RLCD4 320 320 240 k 1 2 1 3 1 4 bias DBS 2 0 LCD Duty and Bias Selection bits DBS2 DBS1 DBS0 Description 0 0 0 1 8 duty 1 4 bias 0 0 1 1 6 duty 1 4 bias 0 1 0 1 5 duty 1 3 bi...

Страница 257: ...fx system clock frequency 1 1 fx system clock frequency LCDABC LCD Automatic Bias Control bit 0 LCD automatic bias is off 1 LCD automatic bias is on BMSEL 2 0 Bias Mode A Time Selection bits BMSEL2 B...

Страница 258: ...tion 0 0 0 0 VLC0 VDD x 16 31 step 0 0 0 1 VLC0 VDD x 16 30 step 0 0 1 0 VLC0 VDD x 16 29 step 0 0 1 1 VLC0 VDD x 16 28 step 0 1 0 0 VLC0 VDD x 16 27 step 0 1 0 1 VLC0 VDD x 16 26 step 0 1 1 0 VLC0 VD...

Страница 259: ...LCD driving resistors for bias LCDEPEN LCD External Bias Path Enable bit 0 Disable 1 Enable LCDBSSRL LCD source Selection Low Register 104CH 7 6 5 4 3 2 1 0 VLC3EN VLC2EN VLC1EN VLC0EN VLC_REG3 VLC_R...

Страница 260: ...tine is served CRC FLAG is not cleared by hardware CRC TYPE 0 3 are not supported Validate is done by comparing the CRC_MNT register and the CRC register value CRC are not automatically initialized yo...

Страница 261: ...C_MNT_H 1074H R W 00H CRC Monitor High Register CRC_MNT_L 1075H R W 00H CRC Monitor Low Register CRC_ADDR_START_H 1079H R W 00H CRC Start Address High Register CRC_ADDR_START_M 107AH R W 00H CRC Start...

Страница 262: ...C interrupt enable RESET_EN Enable CRC reset 0 CRC reset disable 1 CRC reset enable CRC_EN Enable CRC operation it is cleared automatically after the CRC monitoring is finished 0 CRC disable 1 CRC ena...

Страница 263: ...CRC_ADDR_ START 16 R W R W R W R W R W R W R W R W Initial value 00H CRC_ADDR_START_M CRC Start Address Middle Register 107AH 7 6 5 4 3 2 1 0 CRC_ADDR_ START 15 CRC_ADDR_ START 14 CRC_ADDR_ START 13...

Страница 264: ...R_ END 9 CRC_ADDR_ END 8 R W R W R W R W R W R W R W R W Initial value 00H CRC_ADDR_END_L CRC END Address Low Register 107EH 7 6 5 4 3 2 1 0 CRC_ADDR_ END 7 CRC_ADDR_ END 6 CRC_ADDR_ END 5 CRC_ADDR_ E...

Страница 265: ...power down modes to minimize the power consumption of the device In power down mode power consumption is reduced considerably A96G150 provides three kinds of power saving functions such as Main IDLE...

Страница 266: ...rated with sub clock Timer0 4 Operates continuously Halts only when the event counter mode is enabled timer operates normally ADC Operates continuously Stops BUZ Operates continuously Stops USI0 1 Ope...

Страница 267: ...peripherals are operated normally but CPU stops It is released by reset or an interrupt To be released by an interrupt the interrupt should be enabled before IDLE mode If using a reset because the de...

Страница 268: ...es to exit from STOP mode is hardware reset and interrupts The hardware reset re defines all control registers When awaking from STOP mode enough oscillation stabilization time is required to normal o...

Страница 269: ...o 1 the STOP mode is released by a certain interrupt of which interrupt enable flag 1 and the CPU jumps to the relevant interrupt service routine Even if the IE EA bit is cleared to 0 the STOP mode is...

Страница 270: ...e 00H PCON 7 0 Power Control 01H IDLE mode enable 03H STOP mode enable Other Values Normal operation NOTES 1 To enter into IDLE mode PCON must be set to 01H 2 To enter into STOP mode PCON must be set...

Страница 271: ...ter Refer to the Peripheral Registers A96G150 has five types of reset sources as shown in the followings External RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN 1 Low Voltage Reset...

Страница 272: ...unction instead of the RESET IC or the RESET circuits Figure 121 Fast VDD Rising Time Figure 122 Internal RESET Release Timing on Power up VDD nPOR Internal Signal Internal RESETB Oscillation BIT Star...

Страница 273: ...ETB BIT for Reset LSIRC 128kHz 32 LSIRC 128kHz RESET_SYSB Configure Read 250us X 28h 10ms 250us X 40h 16ms F1 Counting for configure option read start after POR is released H LSIRC 128kHz 32 4kHz 250u...

Страница 274: ...x32h Delay section 10ms VDD input voltage must rise over than flash operating voltage for Configure option read Slew Rate 0 025V ms Configure option read point About 1 6V to 1 8V Configure Value is de...

Страница 275: ...the internal reset becomes 1 The reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure 125 Timing Diagram after RESET Figu...

Страница 276: ...2 28V 2 46V 2 68V 2 81V 3 06V 3 21V 3 56V 3 73V 3 91V 4 25V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption LVREN bit is set...

Страница 277: ...g When LVR RESET VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset LSIRC 128kHz 32 LSIRC 128kHz RESET_SYSB Config Read 250us X 28h 10ms 250us X 40h 16ms F1 F1 H LSIRC 128kHz 32 4kHz...

Страница 278: ...s manual 278 20 5 LVI block diagram M U X LVIF LVIEN 2 46V VDD LVIREF Reference Voltage Generator 2 68V 2 81V LVI Circuit LVILS 3 0 3 06V 3 21V 3 56V 3 73V 3 91V 4 25V 2 00V 2 13V 2 28V 1 88V 4 Figure...

Страница 279: ...egister map Table 46 Reset Operation Register Map Name Address Direction Default Description RSTFR E8H R W 80H Reset Flag Register LVRCR D8H R W 00H Low Voltage Reset Control Register LVICR 86H R W 00...

Страница 280: ...chip debugger reset flag bit The bit reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection LVRF Low Voltage Reset flag bit The bit is reset by writing 0 to this bit or by Pow...

Страница 281: ...0 0 0 0 1 61V 0 0 0 1 1 68V 0 0 1 0 1 77V 0 0 1 1 1 88V 0 1 0 0 2 00V 0 1 0 1 2 13V 0 1 1 0 2 28V 0 1 1 1 2 46V 1 0 0 0 2 68V 1 0 0 1 2 81V 1 0 1 0 3 06V 1 0 1 1 3 21V 1 1 0 0 3 56V 1 1 0 1 3 73V 1 1...

Страница 282: ...icator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVIVS 3 0 LVI Level Select LVIVS3 LVIVS2 LVIVS1 LVIVS0 Description 0 0 0 0 Not available 0 0 0 1 Not available 0...

Страница 283: ...egister FEMR Control Register FECR Status Register FESR Time Control Register FETCR Address Low Register x FEARLx Address Middle Register x FEARMx address High Register FEARH They are mapped to SFR ar...

Страница 284: ...sable program or program verify mode 1 Enable program or program verify mode ERASE Enable erase or erase verify mode with VFY 0 Disable erase or erase verify mode 1 Enable erase or erase verify mode P...

Страница 285: ...am mode WRITE Start to program or erase of Flash It is cleared automatically after 1 clock 0 No operation 1 Start to program or erase of Flash READ Start auto verify of Flash It is cleared automatical...

Страница 286: ...st flag Auto cleared when program erase verify starts Active in program erase verify completion 0 No interrupt request 1 Interrupt request WMODE Write mode flag EMODE Erase mode flag VMODE Verify mode...

Страница 287: ...the same least significant bits as the number of bits of page address In auto verify mode address increases automatically by one 2 FEARs are write only register Reading these registers returns 24 bit...

Страница 288: ...ead 24 bit Checksum H M L Read OCD_XDATA FEARH Read OCD_XDATA FEARM Read OCD_XDATA FEARL Set checksum read mode Write OCD_CODE 0xFAAA 0x55 Write OCD_CODE 0xF555 0xA5 Write OCD_XDATA FEMR 0x81 Write OC...

Страница 289: ...L Set checksum read mode Write OCD_CODE 0xFAAA 0x55 Write OCD_CODE 0xF555 0xA5 Write OCD_XDATA FEMR 0x81 Write OCD_CODE FETR 0x00 Write OCD_CODE FECR 0x07 Exit checksum read mode Write OCD_XDATA FECR...

Страница 290: ...hen program or erase starts Timer stops when 10 bit counter is same to FETCR PEVBSY is cleared when program erase or verify starts and set when program erase or verify stops Max program erase time at...

Страница 291: ...tten by byte or page One page is 64 bytes Figure 133 Flash Memory Map Figure 134 Address Configuration of Flash Memory PAGE ADDRESS WORD ADDRESS Program Memory 0x3F 0x00 0x000 0x3FF Page buffer size 6...

Страница 292: ...by byte or page One page is 32 bytes Figure 135 Data EEPROM Memory Map PAGE ADDRESS WORD ADDRESS Program Memory 0x1F 0x00 0x000 0x3F Page buffer size 32Bytes Page 63 Page 62 Page 0 Page 1 10 9 8 7 6 5...

Страница 293: ...ption 7 6 5 4 3 2 1 0 FEMR 4 1 FEMR 5 1 FEMR 2 FECR 6 FECR 7 ERASE VFY PGM VFY OTPE AEE AEF Figure 137 The Sequence of Page Program and Erase of Flash Memory Page Buffer Reset Page Buffer Load 0X00H E...

Страница 294: ...Memory Flash read Enter OCD ISP mode Set ENBDM bit of BCR Enable debug and Request debug mode Read data from Flash Page Buffer Reset Page Buffer Load Configuration Reg 0 Set Erase Latency 500us Page...

Страница 295: ...ommand sequence to activate Flash write erase mode It is composed of sequentially writing data of Flash memory Flash write mode Enable program mode Reset page buffer FEMR 1000_0001 FECR 0000_0010 Sele...

Страница 296: ...erase FECR 0000_1011 Insert one NOP operation Read FESR until PEVBSY is 1 Repeat to until all pages are erased Flash bulk erase mode Enable program mode Reset page buffer FEMR 1000_0001 FECR 0000_001...

Страница 297: ...rom Flash Flash OTP area write mode Enable program mode Reset page buffer FEMR 1000_0001 FECR 0000_0010 Select page buffer FEMR 1000_1001 Write data to page buffer Address automatically increases by t...

Страница 298: ...FEMR 1001_0101 Set page address FEARH FEARM FEARL 20 hx_xxxx Set FETCR Start erase FECR 0000_1011 Insert one NOP operation Read FESR until PEVBSY is 1 Flash program verify mode Enable program mode Se...

Страница 299: ...e mode Table 49 Operation Mode Operation mode Description Flash Flash read Read cell by byte Flash write Write cell by bytes or page Flash page erase Erase cell by page Flash bulk erase Erase the whol...

Страница 300: ...f SFR area Data EEPROM Read Enter OCD ISP mode Set ENBDM bit of BCR Enable debug and Request debug mode Read data from Data EEPROM Enable program mode Enter OCD ISP mode 1 Set ENBDM bit of BCR Enable...

Страница 301: ...rt program FECR 0000_1011 Insert one NOP operation Read FESR until PEVBSY is 1 Repeat step2 to step 8 until all pages are written EEPROM page erase mode Enable program mode Reset page buffer FEMR 0100...

Страница 302: ...ode FEMR 0101_0001 Set FETCR Start bulk erase FECR 0100_1011 Insert one NOP operation Read FESR until PEVBSY is 1 Data EEPROM program verify mode Enable program mode Set program verify mode FEMR 0110_...

Страница 303: ...od of ISP mode 21 4 1 Mode entrance method for ISP Table 50 Mode Entrance Method for ISP TARGET MODE DSDA DSCL DSDA OCD ISP hC hC hC Figure 139 ISP Mode Power on reset RESET P5 5 DSCL P0 1 DSDA P0 0 R...

Страница 304: ...SP mode FLASH Data EEPROM OTP FLASH Data EEPROM OTP DR_P CR_P R W PE BE R W PE BE R W PE BE R W PE BE R W PE BE R W PE BE 0 0 O O O X O O O O X X X X O O O O O O O O O O O O 0 1 O O O X O O O O X X X...

Страница 305: ...52 1 Enable RESETB pin NOTE Code write protection and Vector area protection are disabled at OCD Mode CONFIGURE OPTION 1 ROM Address 0000H A96G150 64K Series 7 6 5 4 3 2 1 0 PAEN PASS2 PASS1 PASS0 Ini...

Страница 306: ...elect Specific Area for Write Protection NOTE When PAEN 1 it is applied PASS2 PASS1 PASS0 Description 0 0 0 0 7Kbytes Address 0100H 03FFH 0 0 1 1 7Kbytes Address 0100H 07FFH 0 1 0 2 7Kbytes Address 01...

Страница 307: ...help a user in generating right results to match target applications ABOV supports entire development ecosystem of the customers 22 1 Compiler ABOV semiconductor does not provide any compiler for A96G...

Страница 308: ...r Yes no 94 97 series only Debug interface OCD 1 OCD 2 Number of break point 4 8 Real time monitoring Yes no OCD 2 only Run flag port Yes no OCD 2 option NOTES 1 A96G150 has 96 series core and OCD 1 i...

Страница 309: ...er Bank 4 CPU Flash Clock Ratio x 1 Pipeline No No 2 stage IF ID EX DHRY Stone Score I8051 1 00 6 0 6 0 8 4 Average Instruction Set Exe Cycle Compare with i8051 x 6 0 x 6 0 x 6 4 Power Consumption DHR...

Страница 310: ...iption OCD 1 Break point MAX 8 PC break only OCD 2 Break point MAX 12 With RAM break Code XDATA IDATA 1 8 16 32bit compare Real time monitoring Code XDATA IDATA Frequency output Examine CPU frequency...

Страница 311: ...evels Series 96 Series 97 Series 94 Series Remark Interrupt Priority 6 Grouped 4 Level Fully 4 Level Fully 4 Level 96 Series IP IP Interrupt Priority Register 94 97 Series IPxL IPxH Interrupt Priority...

Страница 312: ...2 The XSPCR decides whether to use XRAM for Stack Pointer If XSPCR 0 IRAM is available for Stack Pointer If XSPCR 1 XRAM is available for Stack Pointer 3 The XSP decides a position of XRAM Stack Point...

Страница 313: ...d writing Table 58 Debug Feature by Series 96 series 97 series 94 series OCD function OCD 1 OCD 2 OCD 2 Max number of breakpoints 8 8 4 Saving stack in XRAM No Yes Yes Real time monitoring No Yes Yes...

Страница 314: ...ogic power supply pin The OCD emulator supports ABOV s 8051 series MCU emulation The OCD uses two wires interfacing between PC and MCU which is attached to user s system The OCD can read or change the...

Страница 315: ...OCD interface can be found in this section Table 60 introduces features of OCD Table 60 OCD Features Two wire external interface 1 for serial clock input 1 for bi directional serial data bus Debugger...

Страница 316: ...f initialization when powering on the microcontroller To do this users should be able to control the power of the microcontroller VCC or VDD and need to be careful to place a capacitive load such as a...

Страница 317: ...icate a start and an end of the communication More detailed information of this communication protocol is listed below Basic transmission packet A 10 bit packet transmission using two pin interface A...

Страница 318: ...f a packet and is valid when DSDA falls from H to L while External Host maintains DSCL to H After this communication data is transferred and received between a Host and a microcontroller The end bit m...

Страница 319: ...a is allowed to change when DSCL is L If the data changes when DSCL is H the change means START or STOP Figure 147 Bit Transfer on Serial Bus Figure 148 Start and Stop Condition During the OCD communi...

Страница 320: ...ications if a microcontroller needs communication delay or process delay it can request communication delay to the Host Debugger Figure 150 shows timing diagrams where a microcontroller requests commu...

Страница 321: ...rogram A96G150 directly using the E PGM Figure 151 E PGM Single Writer and Pinouts 22 4 2 OCD emulator OCD emulator allows a user to write code on the device too since OCD debugger supports ISP In Sys...

Страница 322: ...g4 and E Gang6 allows a user to program on multiple devices at a time They run not only in PC controlled mode but also in standalone mode without PC control USB interface is available and it is easy t...

Страница 323: ...Flash Programming Pin name Main chip pin name During programming I O Description DSCL P13 I Serial clock pin Input only pin DSDA P11 I O Serial data pin Output port when reading and input port when p...

Страница 324: ...d Wire AND Bi Directional I O Normally it is recommended to place a resister greater than 4 7k for DSCL and DSDA respectively The capacitive load is recommended to be less than 100pF Outside these ran...

Страница 325: ...a user designs a PCB circuit the user should consider the usage of these 4 signal lines for the on board programming Please be careful to design the related circuit of these signal pins because rising...

Страница 326: ...he OCD functions first when they are shared To application circuit P01 DSCL I P00 DSDA I O R1 2k 5k To application circuit R2 2k 5k VDD VSS E PGM E GANG4 E GANG6 VDD VSS DSCL DSDA MCU Four wire Interf...

Страница 327: ...d direct byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 9F S...

Страница 328: ...ct memory to A 1 1 46 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F XRL A di...

Страница 329: ...r data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 A7 MOV Ri data Move immediate to indirect memory 2 1 76 7...

Страница 330: ...TB C Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPL C Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to car...

Страница 331: ...on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indir...

Страница 332: ...2 A5 TRAP Software break command 1 1 A5 In the above table entries such as E8 EF indicate continuous blocks of hex opcodes used for 8 different registers Register numbers of which are defined by the l...

Страница 333: ...A96G150 User s manual Revision history 333 Revision history Revision Date Notes 1 00 2022 06 22 First creation...

Страница 334: ...shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications ABOV and the ABOV logo are trademarks of ABOV All other product or ser...

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