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IM 704420-01E
Explanation of Functions
1
Clock Signal Input
Regenerating the clock signal «See 4.7 for the operating procedure»
The clock signal that is necessary in measuring the D-to-C jitter can be regenerated
by the PLL circuit of the TA120E. You can also measure the time difference by
applying a DVD clock signal to the clock input connector instead of regenerating the
clock signal using the PLL circuit.
Selecting the slope «See 4.1 for the operating procedure»
When using the clock signal that is applied to the clock input connector for measuring
the D-to-C jitter, you can select on which slope (rising edge or falling edge) of the
clock signal to make the measurement.
Adjusting the phase difference «See 4.8 for the operating procedure»
When using the clock signal that is applied to the clock input connector for measuring
the D-to-C jitter, you can adjust the phase difference between the data signal and the
clock signal. You can adjust the phase difference within the range 0 ns to 40 ns.
1.4 Acquisition Conditions for the Input Signal Being Measured
