YOKOGAWA TA120E, User Manual

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1-2
IM 704420-01E
Block Diagram
BI-PHASE
Input
AMP
Buffer
AMP
Buffer
AMP
Buffer
Buffer
Buffer
AMP
EQUALIZED RF/
MONITOR OUT
Equalizer
Slicer
CPU KEY
GP-IB EXT I/O
7 SEG
LED
Trigger
DAC
Programable
Delay
Amplitude
Measure
Phase
Locked
Loop
T/V
Converter
/ A/D
Converter
Meter
DAC
ANALOG
METER
JITTER
DC OUT
LEVEL
DC OUT
EXTERNAL
ARMING IN
INHIBIT
IN
SLICED
RF OUT
Jitter
DC OUT
DAC
Level
DC OUT
DAC
Acquisition
Memory
1 to 2
Acquisition Controller
Signal
Multiplexer
&
Fractional
Pulse
Generator
Compa
rator
RF IN
CLOCK IN
DATA
Controller
1 to 2
Input
AMP
CLOCK
OUT
Buffer
AMP
Buffer
AMP
*1
*2
*3
*2
*1 BI-PHASE measurement function option
*2 Level measurement function option
*3 EXT I/O option
Signal Flow
The TA120E is a jitter meter for optical disks. It measures the 3T jitter
*1
and D-to-C
jitter
*2
of optical disks that employ the EFM method.
The amplitude of the RF signal that is input through the RF input connector (RF IN) is
equalized (made into ON/OFF signals) by the equalizer. Then, the signal is converted
into binary values through the slicer circuit, thus becoming a data signal. The signal
multiplexer selects either the clock signal or the data signal or both according to the
measurement function (measurement item) that is selected. The acquisition controller
controls the acquisition of measured values according to the external arming signal
(EXT ARM signal) or the inhibit signal (INHIBIT Signal). The fractional pulse
generator generates fractional pulses from the signal that was selected by the signal
multiplexer according to the acquisition controller’s control. The pulse width of the
fractional pulse is converted into voltage by the time-voltage converter (T/V converter)
and then digitized using an A-to-D converter. Finally, the measured value is
generated and stored in the acquisition memory.
The RF signal and clock signal are necessary in order to measure the D-to-C jitter. In
some cases the clock signal is input through the clock input connector (CLOCK IN),
and in other cases the clock signal is regenerated by the PLL (Phased Locked Loop)
circuit based on the RF (data) signal. You can select either method. When applying a
clock signal to the clock input connector, you can adjust the phase difference between
the clock signal and the RF (data) signal using the programmable delay circuit. You
can adjust the phase difference by observing the analog meter.
The TA120E computes the data in the acquisition memory at high-speeds and
determines the jitter. The jitter that is calculated is displayed on the analog meter and
the 7-segment LED display.
*1 Pulse width jitter of the 3T data signal of a CD.
*2 Time difference jitter between the data signal and clock signal of a DVD.
1.1 System Configuration and Block Diagram