ZC706 Evaluation Board User Guide
3
UG954 (v1.5) September 10, 2015
04/24/2013
1.2
Chapter 1, ZC706 Evaluation Board Features
linked to their respective sections in the book.
, and
were replaced. Table 1-2 was removed because it was a duplicate of
Switch SW11 Configuration Option Settings
was added.
Connector JTAG Bypass, page 33
was updated. Default lane size information below
was changed.
PCI Express Lane Size Select Jumper J19
was
added. The names of pins 18 and 19 changed in
. The address of I
2
C bus
PMBUS_DATA/CLOCK changed in
. Reference designator DS35 was added
to
section are now linked to
. SW13 information was added to the section
In
, J5 pin H22 changed to XC7Z045 (U1) pin AH26 and H23 changed to
AH27. The section
ZC706 Board Power System, page 72
was added. Voltage levels
were changed in
.
was modified and
was added.
Appendix A, Default Switch and Jumper Settings
: The SW11 selection in
changed.
Appendix G, Regulatory and Compliance Information
: A link to the master answer
record was added.
07/31/2013
1.3
Updated
. Replaced the master User Constraints File (UCF) list in
Appendix C, Master Constraints File Listing
with the master Xilinx Design
Constraints (XDC) list. Updated references throughout the document.
04/28/2015
1.4
Updated “LMZ22000 Family Regulator Description” to
. Updated
,
,
through
,
through
, and
. Updated
Appendix C, Master Constraints File Listing
09/10/2015
1.5
Updated J48 header jumper setting (third row in
Date
Version
Revision