Xilinx ZC706, User Manual

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ZC706 Evaluation Board User Guide www.xilinx.com 50
UG954 (v1.5) September 10, 2015
Feature Descriptions
Table 1-22 lists the USB connections between the XC7Z045 AP SoC PS Bank 501 and the
CP2103 UART bridge.
Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP
drivers [Ref 21] .
For additional information on the Zynq-7000 AP SoC device UART controller, see Zynq-7000
All Programmable SoC Overview ( DS190 ) and Zynq-7000 All Programmable SoC Technical
Reference Manual ( UG585 ).
HDMI Video Output
[ Figure 1-2 , callout 18]
The ZC706 evaluation board provides a high-definition multimedia interface (HDMI®)
video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U53. The HDMI
transmitter U53 is connected to the XC7Z045 AP SoC PL-side banks 12 and 13 and its output
is provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports
1080P 60Hz, YCbCr 4:4:4 encoding via 24-bit input data mapping.
The ZC706 evaluation board supports the following HDMI device interfaces:
• 24 data lines
• Independent VSYNC, HSYNC
• Single-ended input CLK
• Interrupt Out pin to XC7Z045 AP SoC
Table 1-21: USB Connector J21 Pin Assignments and Signal Definitions
USB Connector (J21)
Net Name Description
CP2103GM (U52)
Pin Name Pin Name
1 VBUS USB_UART_VBUS +5V VBUS Powered
7 REGIN
8 VBUS
2 D_N USB_UART_D_N Bidirectional differential serial data (N-side) 4 D –
3 D_P USB_UART_D_P Bidirectional differential serial data (P-side) 3 D +
5 GND USB_UART_GND Signal ground
2 GND1
29 CNR_GND
Table 1-22: XC7Z045 AP SoC to CP2103 Connections
XC7045 AP SoC (U1)
Schematic Net
Name
CP2103GM Device (U52)
Pin Name Bank PIN Function Direction IOSTANDARD PIN Function Direction
PS_MIO48 501 C19 TX Output LVCMOS18 USB_UART_RX 24 RXD Input
PS_MIO49 501 D18 RX Input LVCMOS18 USB_UART_TX 25 TXD Output
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