Xilinx ZC706, User Manual

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ZC706 Evaluation Board User Guide www.xilinx.com 48
UG954 (v1.5) September 10, 2015
Feature Descriptions
The Ethernet connections from the XC7Z045 AP SoC at U1 to the 88E1116R PHY device at
U51 are listed in Table 1-20 .
Ethernet PHY Clock Source
A 25.00 MHz 50 ppm crystal at X1 is the clock source for the 881116R PHY at U51.
Figure 1-20 shows the clock source.
Table 1-19: Board Connections for PHY Configuration Pins
U51 Pin Setting Configuration
CONFIG (64) VCCP1V8 PHYAD[1]=1 PHYAD[0]=1
CONFIG1 (1) PHY_LED0 PHYAD[3]=0 PHYAD[2]=1
CONFIG2 (2)
GND ENA_XC=0 PHYAD[4]=0
PHY_LED0 ENA_XC=0 PHYAD[4]=1
VCCP1V8 ENA_XC=1 PHYAD[4]=1
CONFIG3 (3)
GND RGMII_TX=0 RGMII_RX=0
PHY_LED0 RGMII_TX=0 RGMII_RX=1
PHY_LED1 RGMII_TX=1 RGMII_RX=0
VCCP1V8 RGMII_TX=1 RGMII_RX=1
Table 1-20: Ethernet Connections, XC7Z045 AP SoC to the PHY Device
XC7Z045 (U1) Pin
Schematic
Net Name
M88E1116R PHY U51
Pin Name Bank
Pin
Number
Pin Name
PS_MIO53 501 C18 PHY_MDIO 45 MDIO
PS_MIO52 501 D19 PHY_MDC 48 MDC
PS_MIO16 501 L19 PHY_TX_CLK 60 TX_CLK
PS_MIO21 501 J19 PHY_TX_CTRL 63 TX_CTRL
PS_MIO20 501 M20 PHY_TXD3 62 TXD3
PS_MIO19 501 J20 PHY_TXD2 61 TXD2
PS_MIO18 501 K20 PHY_TXD1 59 TXD1
PS_MIO17 501 K21 PHY_TXD0 58 TXD0
PS_MIO22 501 L20 PHY_RX_CLK 53 RX_CLK
PS_MIO27 501 G20 PHY_RX_CTRL 49 RX_CTRL
PS_MIO26 501 M17 PHY_RXD3 55 RXD3
PS_MIO25 501 G19 PHY_RXD2 54 RXD2
PS_MIO24 501 M19 PHY_RXD1 51 RXD1
PS_MIO23 501 J21 PHY_RXD0 50 RXD0
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