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SMP7500 Theory of Operation
59
D
EVICE
T
RANSFERS
(R
EAD
M
ODE
)
When read transfers from the UUT are desired the SMP7500 will receive data from the UUT. If
output clocks are required they must be setup and enabled to drive the F/P CLK lines. Data will be
latched into the I/O Data Buffer either transparently, or upon a F/P CLK signal, or a selected VXI
register write.
D
IRECTION
Direction of transfer is controlled either from the front panel connector or from the PORT’s
Control Register PORT Inn/Out Select Bit. Controlling the direction of the PORT
programmatically overrides the F/P CLK lines. If the direction of the PORT is programmatically
set to an input, the PORT direction will be a function of the F/P I/O control line. The PORT
Inn/Out Select Bit is ORed with the corresponding I/O signal from the front panel connector.
C
LOCK
E
NABLE
The Input Clock is selected when the SMIP
II
module receives the VXI register write that sets the
PORT’s Control Register PORT Clock to Input Port Select Bits. The Input Clock may be selected
from either a F/P CLK line, or Relay Register Write Event. The Input Clock Polarity is set in the
same fashion.
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