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SMP7500 Introduction
13
A single SMP7500 provides 96 open collector digital I/O line that are configurable as inputs or
outputs in twelve groups of 8 channels each. The module can drive up to 60 V with sink current of
up to 300 mA per channel. Each group of 8 bits is referred as a PORT. Each PORT can be
configured as an input port or an output port under program control. The SMP7500 has the
flexibility to configure the sourcing of the input and output clocks from either the front panel (F/P
GND_I/O) (one input per PORT), or via a VXI A24/A32 control register. There is also a Global
Clock Line from the front panel that may be user selected via hardware jumpers to drive selected
PORT clocks. By using the appropriate clocking configuration, very large numbers of channels
may by synchronized to collect or present data to a UUT (unit under test).
Each clock input is internally pulled to a logic high level and has an RC termination network to
reduce multiple clocking edges due to line ringing. The RC network consists of a 120
Ω
resistor in
series with a 100 pF capacitor, giving a time constant of 12 ns.
The SMP7500 can be combined with any member of the SMIP
II
family to form a customized and
highly integrated instrument/switch.
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