VXI Technology, Inc.
48
SMP7500 Programming
E
XAMPLE
O
F
A
P
ORT
O
UTPUT
W
RITE
T
O
A
P
ORT
I
NPUT
R
EAD
For this example, data from Port 0 to Port 2 will be configured and transfered through a
wrap-around cable. The wrap-around cable pin outs used are as defined in Table 3-3. The data to
be sent from Port 0 is 68. Port 0 will source the F/P CLK and Port 2 will receive the clock signal.
USER CONNECTOR
GND_I/O
DATA
GND_CLK
GLOBAL
CLK
47k
User Selectable
HW Jumpers
Off To All Other Ports
47K
User Selectable
HW Jumpers
120
100pf
2
2
Polarity
Output
Drivers
Over
Current
Sense /
Control
Over Current Sense
Shut Down
ISENSE
R/B
Control
Writes to
Specific Port
Addresses
Control
Control
Relay Req. 000Ch Write Event
WR EVENT
R/B
I/O Data
Buffer
Data
Relay Req. 000Ch Write Event
SMIP INTERFACE
MODULE
DATA
ADDRESS
CONTROL
BUSYN
TTL
TRIGGER
BUS
0-7
DATA
ADDRESS
CONTROL
VXI
B
A
CKPLANE
SMP7500 MODULE
Over Current
Reset
Control
Trace
Memory
PORT 0
USER CONNECTOR
GND_I/O
(Left Floating)
DATA
GND_CLK
GLOBAL
CLK
47k
User Selectable
HW Jumpers
22
Off To All Other Ports
47K
User Selectable
HW Jumpers
120
100pf
2
2
200K
33K
R/B
Control
Writes to
Specific Port
Addresses
Control
Control
Relay Req. 000Ch Write Event
WR EVENT
R/B
I/O Data
Buffer
Data
Control
PORT 2
(Set to 0)
Backplane
Load
Immediate
(Set)
Enable
(Set)
22
F
IGURE
3-4:
W
RITE
/R
EAD
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