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SMP7500 Programming
39
CONTROL REGISTER OVER CURRENT RESET – Read and Write
D15-D0
Over Current Reset Bits
[15:0]
Set to 0 for normal Over Current Sense Line operation. Set to 1 to
reset the corresponding Over Current Sense Line.
Note that the operation of the Over Current Reset Bits is edge
sensitive. The reset of an Over Current Line is initiated on the rising
edge of the corresponding Over Current Reset Bit. If an over current
situation still exists after the reset has been initiated, the PORT/s will
remain off until the over current cause is removed, and another reset
edge is generated. This register’s read back will indicate the last
value written to the reset register.
Pon state = 0
CONTROL REGISTER F/P IN/OUTN LINES – Read
D5-D0
F/P In/Outn Lines [5:0]
Read Back
The state of these lines is dependent on the setup of the F/P In/Outn
lines 5 thru 0. If the F/P lines are used as GND, then the read back
lines are pulled to a logic 1. If the F/P lines are used as inputs or
outputs, then a read back of this register shows their present state.
Pon state = Dependent
D7-D6
Unused
These bits are unused.
D13-D8
F/P In/Outn Lines [11:6]
Read Back
The state of these lines is dependent on the setup of the F/P In/Outn
lines 11 thru 6. If the F/P lines are used as GND, then the read back
lines are pulled to a logic 1. If the F/P lines are used as inputs or
outputs, then a read back of this register shows their present state.
Pon state = Dependent
D15-D14
Unused
These bits are unused.
CONTROL REGISTER F/P CLK LINES – Read
D5-D0
F/P CLK Lines [5:0] Read
Back
The state of these lines is dependent on the setup of the F/P CLK
lines 5 thru 0. If the F/P lines are used as GND, then the read back
lines are pulled to a logic 1. If the F/P lines are used as inputs or
outputs, then a read back of this register shows their present state.
The state of the Global Clock line may also be read the line/s are
hardware jumpered to the Global Clock line.
Pon state = Dependent
D7-D6
Unused
These bits are unused.
D13-D8
F/P CLK Lines [11:6]
Read Back
The state of these lines is dependent on the setup of the F/P CLK
lines 11 thru 6. If the F/P lines are used as GND, then the read back
lines are pulled to a logic 1. If the F/P lines are used as inputs or
outputs, then a read back of this register shows their present state.
The state of the Global Clock line may also be read the line/s are
hardware jumpered to the Global Clock line.
Pon state = Dependent
D15-D14
Unused
These bits are unused.
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