Callgrind: a call-graph generating cache and branch prediction profiler
--separate-threads=<no|yes> [default:
no]
This option specifies whether profile data should be generated separately for every thread. If yes, the file names get
"-threadID" appended.
--separate-callers=<callers> [default:
0]
Separate contexts by at most <callers> functions in the call chain. See
Avoiding cycles
.
--separate-callers<number>=<function>
Separate
number
callers for
function
. See
Avoiding cycles
.
--separate-recs=<level> [default:
2]
Separate function recursions by at most
level
levels. See
Avoiding cycles
.
--separate-recs<number>=<function>
Separate
number
recursions for
function
. See
Avoiding cycles
.
--skip-plt=<no|yes> [default:
yes]
Ignore calls to/from PLT sections.
--skip-direct-rec=<no|yes> [default:
yes]
Ignore direct recursions.
--fn-skip=<function>
Ignore calls to/from a given function.
E.g. if you have a call chain A > B > C, and you specify function B to be
ignored, you will only see A > C.
This is very convenient to skip functions handling callback behaviour. For example, with the signal/slot mechanism
in the Qt graphics library, you only want to see the function emitting a signal to call the slots connected to that signal.
First, determine the real call chain to see the functions needed to be skipped, then use this option.
6.3.5. Simulation options
--cache-sim=<yes|no> [default:
no]
Specify if you want to do full cache simulation.
By default, only instruction read accesses will be counted ("Ir").
With cache simulation, further event counters are enabled: Cache misses on instruction reads ("I1mr"/"ILmr"), data
read accesses ("Dr") and related cache misses ("D1mr"/"DLmr"), data write accesses ("Dw") and related cache misses
("D1mw"/"DLmw"). For more information, see
Cachegrind: a cache and branch-prediction profiler
.
--branch-sim=<yes|no> [default:
no]
Specify if you want to do branch prediction simulation. Further event counters are enabled: Number of executed
conditional branches and related predictor misses ("Bc"/"Bcm"), executed indirect jumps and related misses of the
jump address predictor ("Bi"/"Bim").
6.3.6. Cache simulation options
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