
6 F 2 T 0 1 7 2
Current (amps)
Time (s)
OC2
OC3
Fuse
OC1
Figure 2.2.3 Staged Definite Time Protection
2.2.3
Scheme Logic
As shown in Figure 2.2.4 to Figure 2.2.9, OC2 to OC4 and EF2 to EF4 have independent scheme
logics. OC2 and EF2 provide the same logic of OC1 and EF1. OC3 and EF3 give trip signals OC3
TRIP and EF3 TRIP through delayed pick-up timers TOC3 and TEF3. OC4 and EF4 are used to
output alarm signals OC4 ALARM and EF4 ALARM. Each trip and alarm can be blocked by
incorporated scheme switches [OC2EN] to [EF4EN] and binary input signals OC2 BLOCK to EF4
BLOCK. OC*-D and EF*-D elements can be also blocked by the scheme switches [OC*-2F] and
[EF*-2F]. See Section 2.9.
≥
1
OC2 TRIP
OC2 BLOCK
1
0.00 - 300.00s
&
TOC2
t
0
"IEC"
"IEEE"
+
"ON"
[OC2EN
+
C
B
A
OC2
-D
&
t
0
≥
1
&
t
0
≥
1
&
C
B
A
&
&
"US"
"C"
≥
1
≥
1
≥
1
&
≥
1
106
OC2-A TRIP
107
108
105
OC2-B TRIP
OC2-C TRIP
54
OC2-A
55
56
OC2-B
OC2-C
"D"
OC2
-I
&
[MOC2]
+
[OC2-2F]
ICD
“Block”
Figure 2.2.4
Phase Overcurrent Protection OC2
18
Summary of Contents for GRE110
Page 183: ...6 F 2 T 0 1 7 2 Appendix B Signal List 184 ...
Page 191: ...6 F 2 T 0 1 7 2 Appendix C Event Record Items 192 ...
Page 196: ...6 F 2 T 0 1 7 2 Appendix D Binary Output Default Setting List 197 ...
Page 199: ...6 F 2 T 0 1 7 2 Appendix E Relay Menu Tree 200 ...
Page 210: ...6 F 2 T 0 1 7 2 Appendix F Case Outline 211 ...
Page 211: ...6 F 2 T 0 1 7 2 Case Outline for model 400 401 420 421 820 and 821 212 ...
Page 212: ...6 F 2 T 0 1 7 2 Case Outline for model 402 and 422 213 ...
Page 213: ...6 F 2 T 0 1 7 2 Appendix G Typical External Connection 214 ...
Page 245: ...6 F 2 T 0 1 7 2 Appendix J Return Repair Form 246 ...
Page 249: ...6 F 2 T 0 1 7 2 Customer Name Company Name Address Telephone No Facsimile No Signature 250 ...
Page 250: ...6 F 2 T 0 1 7 2 Appendix K Technical Data 251 ...
Page 256: ...6 F 2 T 0 1 7 2 Appendix L Symbols Used in Scheme Logic 257 ...
Page 259: ...6 F 2 T 0 1 7 2 Appendix M Modbus Interoperability 260 ...
Page 289: ...6 F 2 T 0 1 7 2 Appendix N IEC60870 5 103 Interoperability 290 ...
Page 296: ...6 F 2 T 0 1 7 2 Appendix O PLC Default setting 297 ...
Page 298: ...6 F 2 T 0 1 7 2 Appendix P Inverse Time Characteristics 299 ...
Page 304: ...6 F 2 T 0 1 7 2 Appendix Q IEC61850 Interoperability 305 ...