53
SLWS245B – MAY 2014 – REVISED FEBRUARY 2017
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Copyright © 2014–2017, Texas Instruments Incorporated
8.5.1.1 BIAS SETTINGS
Optimum TRF7322 bias settings used in the performance measurements are shown in
.
Table 16. Register Settings With Optimized Bias Set Used in the Performance Measurement.
REGISTER
BITS
TYPICAL OPERATING
MODE [256MHz-2GHz],
INT MODE
TYPICAL OPERATING
MODE [2GHz - 3GHz],
INT MODE
TYPICAL OPERATING
MODE [3GHz -
4.1GHz], INT MODE
LOW POWER MODE,
INT MODE
FRACTIONAL MODE
REGISTER 1
RDIV
x
x
x
x
x
REGISTER 1
REF_INV
0
0
0
0
0
REGISTER 1
NEG_VCO
1
1
1
1
1
REGISTER 1
ICP
0
0
0
0
0
REGISTER 1
ICPDOUBLE
0
0
0
0
0
REGISTER 1
CAL_CLK_SEL
13
13
13
13
15
REGISTER 2
NINT
x
x
x
x
x
REGISTER 2
PLL_DIV_SEL
x
x
x
x
x
REGISTER 2
PRSC_SEL
x
x
x
x
x
REGISTER 2
VCO_SEL
x
x
x
x
x
REGISTER 2
VCO_SEL_MODE
x
x
x
x
x
REGISTER 2
CAL_ACC
0
0
0
0
0
REGISTER 2
EN_CAL
1
1
1
1
1
REGISTER 3
NFRAC
0
0
0
0
x
REGISTER 4
PWD_PLL
0
0
0
0
0
REGISTER 4
PWD_CP
0
0
0
0
0
REGISTER 4
PWD_VCO
0
0
0
0
0
REGISTER 4
PWD_VCO_MUX
0
0
0
0
0
REGISTER 4
PWD _DIV124
0
0
0
0
0
REGISTER 4
PWD_PRESC
0
0
0
0
0
REGISTER 4
PWD_OUTBUF
0
0
0
1
0
REGISTER 4
PWD_LO_DIV
0
0
0
1
0
REGISTER 4
PWD_TX_DIV
0
0
0
0
0
REGISTER 4
PWD_MOD
0
0
0
0
0
REGISTER 4
EN_EXTVCO
0
0
0
0
0
REGISTER 4
EN_ISOURCE
0
0
0
0
1
REGISTER 4
LD_ANA_PREC
0
0
0
0
3
REGISTER 4
CP_TRISTATE
0
0
0
0
0
REGISTER 4
SPEEDUP
0
0
0
0
0
REGISTER 4
LD_DIG_PREC
0
0
0
0
0
REGISTER 4
MOD_ORD
5
5
5
5
4
REGISTER 4
DITH_SEL
0
0
0
0
0
REGISTER 4
DEL_SD_CLK
2
2
2
2
0
REGISTER 4
EN_FRAC_MODE
0
0
0
0
1
REGISTER 5
IB_MOD_GM
3
3
2
0
3
REGISTER 5
IB_MOD_LO
0
1
0
0
0
REGISTER 5
VCO_BIAS
15
15
15
15
15
REGISTER 5
VCOBUF_BIAS
2
2
2
2
2
REGISTER 5
OUTBUF_BIAS
2
2
2
0
2
REGISTER 5
VCOMUX_BIAS
2
2
2
2
2
REGISTER 5
VCO_CAL_IB
0
0
0
0
0
REGISTER 5
VCO_CAL_REF
3
3
3
3
3
REGISTER 5
VCO_AMPL_CTRL
0
0
0
0
0
REGISTER 5
VCO_VB_CTRL
3
3
3
3
3
REGISTER 5
EN_LD_ISOURCE
0
0
0
0
0