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SLWS245B – MAY 2014 – REVISED FEBRUARY 2017
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Copyright © 2014–2017, Texas Instruments Incorporated
Table 10. Register 4
Register 4
Bit Name
Reset Value
Description
Bit0
ADDR<0>
0
Register Address Bits
Bit1
ADDR<1>
0
Bit2
ADDR<2>
1
Bit3
ADDR<3>
1
Bit4
ADDR<4>
0
Bit5
PWD_PLL
0
Power -down all PLL blocks: (1 = off)
Bit6
PWD_CP
0
Power-down Charge Pump: (1=off)
Bit7
PWD_VCO
0
Power-down VCO: (1=off)
Bit8
PWD_VCO_MUX
0
Power-down VCO Mux blocks: (1=off)
Bit9
PWD _DIV124
0
Power-down the div 1,2,4 in the PLL f/b path: (1=off)
Bit10
PWD_PRESC
0
Power-down Prescaler: (1=off)
Bit11
RSV
1
Reserved
Bit12
PWD_OUTBUF
1
Power-down Ouptut Buffer: (1=off)
Bit13
PWD_LO_DIV
1
Power-down LO divider block: (1=off)
Bit14
PWD_TX_DIV
1
Power-down TX divider block: (1=off)
Bit15
PWD_MOD
1
Power-down modulator block: (1=off)
Bit16
EN_EXTVCO
0
Enable external VCO input buffer: (1 = enabled)
Bit17
RSV
0
Reserved
Bit18
EN_ISOURCE
0
Enable offset current at CP output (frac-n mode only).
Bit19
LD_ANA_PREC<0>
0
Control precision of Analog Lock Detector:
[00] = H/H (High), [01] = L/L (Low), [10] = H/L , [11] = L/L
Bit20
LD_ANA_PREC<1>
0
Bit21
CP_TRISTATE<0>
0
Set the charge pump output in Tristate mode:
[00] = Off, [01] = Down, [10] = Up, [11] = Tristate
Bit22
CP_TRISTATE<1>
0
Bit23
SPEEDUP
0
Enable fast turn on/off time of bias blocks.
Bit24
LD_DIG_PREC
0
Lock detector precision (increases sampling time if set to 1)
Bit25
MOD_ORD<0>
1
Modulator order (1-4). Not used in integer mode
(defaul 3rd order + dither)
Bit26
MOD_ORD<1>
0
Bit27
MOD_ORD<2>
1
Bit28
DITH_SEL
0
Dither Mode: [0] = pseudo-random, [1] = constant
Bit29
DEL_SD_CLK<0>
0
DS modulator clock delay. Frac-n mode only.
[00] = Min delay, [11] = max delay
Bit30
DEL_SD_CLK<1>
1
Bit31
EN_FRAC_MODE
0
Enable Frac-n mode when set to 1