C4
NS
R4
0R
C3
150pF
R3
1.5K
R2
6.49K
C2
2.2nF
C1
150pF
CP_OUT
VTUNE
PFD
Charge
Pump
LO Div
DMP
4/5 8/9
TX
Quad
Div
N Div
RDIV
Ext
Loop
Filter
LO_DIV_SEL
TX_DIV_SEL
PLL DIV
PLL_DIV_SEL
PRSC_SEL
NINT
Ext VCO/
Ext LO
O°
9O°
VTUNE
C
P
_
O
U
T
f
PFD
f
REF
f
VCO
f
LO
f
TX
SDM
NFRAC_DIV
37
SLWS245B – MAY 2014 – REVISED FEBRUARY 2017
Product Folder Links:
Copyright © 2014–2017, Texas Instruments Incorporated
Feature Description (continued)
Figure 132. PLL Architecture
8.3.5 External VCO
An external LO or VCO signal may be applied. If an external LO is used the internal PLL can be powered down.
Alternatively, dividers, phase-frequency detector, and charge pump can remain enabled and may be used to
control the V
TUNE
of an external VCO. EN_EXTVCO is used to select the internal or external VCO.
8.3.6 Loop Filter
Loop filter design is critical for achieving low closed loop phase noise. Complete modulator performance data has
been measured using integer mode loop filter. The integer mode loop filter was designed considering loop
bandwidth 40 kHz and f
PFD
2.56 MHz. Phase margin of 60 degrees was considered. Refer to TRF3722EVM
User’s Guide to obtain the details on TRF3722 loop component calculations.
shows integer loop filter.
Figure 133. Integer Loop Filter