Texas Instruments TRF3722 EVM Manual Download Page 39

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VCO, Stepsize

TX, Stepsize

PFD

x TX DIV

PLL DIV

LO DIV x

TX DIV x

PLL DIV = Ceiling

= Ceiling

3000 MHz

çè

TRF3722

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SLWS245B – MAY 2014 – REVISED FEBRUARY 2017

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8.4 Device Functional Modes

8.4.1 Selecting PLL Divider Values

With reference to the PLL architecture illustrated in

Figure 132

, operation of the PLL requires TX_DIV_SEL /

LO_DIV_SEL, PLL_DIV_SEL, RDIV, NINT, NFRAC and PRSC_SEL bits to be calculated.

TX_DIV_SEL / LO_DIV_SEL

The LO to the integrated modulator (ƒ

) and additional LO output (ƒ

) frequency is related to f

VCO

according to the following:

= f

VCO

/ TX DIV

= f

VCO

/ LO DIV

Where TX DIV and LO DIV are related to TX_DIV_SEL and LO_DIV_SEL as:

TX_DIV_SEL / LO_DIV_SEL

TX_DIV / LO_DIV

FREQUENCY RANGE

TX_DIV_SEL = 0

TX DIV = 1

2050 MHz

≤

4100 MHz

TX_DIV_SEL = 1

TX DIV = 2

1025 MHz

≤

2050 MHz

TX_DIV_SEL = 2

TX DIV = 4

512.5 MHz

≤

1025 MHz

TX_DIV_SEL = 3

TX DIV = 8

256.25 MHz

≤

512.5 MHz

LO_DIV_SEL = 0

LO DIV = 1

2050 MHz

≤

4100 MHz

LO_DIV_SEL = 1

LO DIV = 2

1025 MHz

≤

2050 MHz

LO_DIV_SEL = 2

LO DIV = 4

512.5 MHz

≤

1025 MHz

LO_DIV_SEL = 3

LO DIV = 8

256.25 MHz

≤

512.5 MHz

PLL_DIV_SEL

Given f

VCO

, select PLL_DIV_SEL so that the division ratio PLL DIV limits the input frequency to the

prescaler , f

DMP

, is limited to a maximum of 3000 MHz.

PLL DIV = min(1, 2, 4) such that f

DMP

≤

3000 MHz

PLL DIV is related to PLL_DIV_SEL according to the following equation:
PLL_DIV = 2

PLL_DIV_SEL

This calculation can be restated as

Equation 6

(6)

For both integer and fractional mode it is preferable to operate the f

PFD

at the highest possible frequency

determined by the required frequency step of the RFOUT or LO_OUT. In Integer mode, select the maximum
f

PFD

according to

Equation 7

(7)

In Fractional mode, small RF stepsize can be obtained through the fractional divider. In this case, the highest
f

PFD

frequency should be selected according to the reference clock and system requirements.

Summary of Contents for TRF3722 EVM

Page 1: ...t LO Output Supports divide by 1 2 4 8 Modulator Low Power and High Gain Modes Multiple Power Down Modes 2 Applications Wireless Infrastructure CDMA IS95 UMTS CDMA2000 TD SCDMA LTE TD LTE LTE Advanced TDMA GSM EDGE MC GSM Point to Point Microwave Point to Multipoint Microwave Software Defined Radios RF Repeaters Distributed Antenna Systems 3 Description The TRF3722 is a high performance direct con...

Page 2: ...Characteristics Power Dissipation 31 7 Parameter Measurement Information 33 7 1 Serial Interface Timing Diagram 33 8 Detailed Description 35 8 1 Overview 35 8 2 Functional Block Diagram 35 8 3 Feature Description 36 8 4 Device Functional Modes 39 8 5 Register Maps 42 9 Application and Implementation 55 9 1 Application Information 55 9 2 Typical Application 55 10 Power Supply Recommendations 58 11 ...

Page 3: ...ts Incorporated 5 Pin Configuration and Functions RGZ Package 48 Pin VQFN Top View Pin Functions PIN I O DESCRIPTION NAME NO BBI_N 29 I BB in phase input negative BBI_P 27 I BB in phase input positive BBQ_N 8 I BB quadrature input negative BBQ_P 10 I BB quadrature input positive CLK 48 I Serial interface clock input digital input CP_OUT 41 O Charge pump output DATA 47 I Serial interface data input...

Page 4: ... device at these or any other conditions beyond those indicated under Recommended Operating Conditions Exposure to absolute maximum rated conditions for extended periods may affect device reliability 6 Specifications 6 1 Absolute Maximum Ratings over operating free air temperature range unless otherwise noted 1 MIN MAX UNIT Supply voltage All VCC except VCC_TK 0 3 3 6 V VCC_TK 0 3 5 5 Digital I O ...

Page 5: ...DITIONS MIN TYP MAX UNIT DC PARAMETERS ICC 3 3 V Supply Current Typical Operating Mode LO out Off 328 1 mA Typical Operating Mode LO out On 374 mA ICC_TK 5 V Supply Current 21 mA PDISS Total Power Dissipation Typical Operating Mode LO out Off 1 18 W Typical Operating Mode LO out On 1 34 W Low Power Mode Mod LO out Off 0 91 W IPD Power Down Current Hardware Power Down 76 mA Serial interface Power D...

Page 6: ...ain Mode 3 dB Gain Flatness In 300 MHz bandwidth 0 5 0 5 dB OP1dB Output Compression Point 13 dBm OIP3 Output 3rd Order Intercept Point fBB 4 5 5 5 MHz 29 5 dBm OIP2 Output 2nd Order Intercept Point fBB 4 5 5 5 MHz 57 dBm SBS Unadj Side Band Suppression 54 5 dBc CF Unadj Carrier Feed through 57 dBm NSDO Output Noise Spectral Density BB inputs terminated on 50 Ω 158 dBm Hz HD2LO LO Second Harmonic ...

Page 7: ...53 dBc HD3BB Baseband Third Harmonic Measured at fLO 3 x fBB 68 dBc IQ MODULATOR ƒLO 3600 MHz G Gain Typical Operating Mode 2 dB High Gain Mode 0 4 dB OP1dB Output Compression Point 8 7 dBm OIP3 Output 3rd Order Intercept Point FBB 4 5 5 5 MHz 24 5 dBm OIP2 Output 2nd Order Intercept Point FBB 4 5 5 5 MHz 45 5 dBm SBS Unadj Side Band Suppression 31 5 dBc CF Unadj Carrier Feed through 39 5 dBm HD2L...

Page 8: ... MHz VTUNE 1 1 V 10 kHz 80 dBc Hz 100 kHz 115 1 MHz 141 10 MHz 156 40 MHz 158 LO OUTPUT fOUT Typical output frequency range 2 Divide by 1 2050 4100 MHz Divide by 2 1025 2050 Divide by 4 512 5 1025 Divide by 8 256 25 512 5 PLO Output power SE at 1800 MHz OUTBUF_BIAS 2 1 dBm External VCO input Frequency Range 250 4200 MHz External VCO Input Level 10 0 10 dBm CLOSE LOOP PLL OR VCO Integrated Phase No...

Page 9: ...e HD3BB Baseband thrid harmonic High Side Low Side D e s i r e d S i g n a l U n w a n t e d S i d e b a n d 3 r d O r d e r I M 2 n d O r d e r I M Freq H D 2B B H D 3B B L O 3 F B B 1 L O 3 F B B 2 L O 3 F B B 2 L O 3 F B B 1 L O 2 F B B 1 L O 2 F B B 2 L O 2 F B B 2 L O 2 F B B 1 9 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedb...

Page 10: ...0 2000 2500 3000 3500 4000 4500 10 8 6 4 2 0 2 4 6 D218 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 10 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 7 Typical Characteristics Output Power Unless specified all plots were created using TRF3722EVM VCC 3 3 V VCC_TK 5 V TA 25...

Page 11: ...0 1500 2000 2500 3000 3500 4000 4500 10 8 6 4 2 0 2 4 6 D004 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 11 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 8 Typical Characteristics Gain Unless specified all plots were created using TRF3722EVM VCC 3 3 V VCC_TK 5 V TA 25 C ...

Page 12: ...Frequency MHz OIP3 dBm 0 500 1000 1500 2000 2500 3000 3500 4000 4500 16 18 20 22 24 26 28 30 32 34 D010 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 12 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 9 Typical Characteristics OIP3 Unless specified all plots were created usi...

Page 13: ...cy MHz OIP2 dBm 0 500 1000 1500 2000 2500 3000 3500 4000 4500 30 35 40 45 50 55 60 65 70 D022 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 13 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 10 Typical Characteristics OIP2 Unless specified all plots were created using TRF372...

Page 14: ...qC TA 25qC TA 85qC Frequency MHz OP1dB dBm 0 500 1000 1500 2000 2500 3000 3500 4000 4500 2 0 2 4 6 8 10 12 14 16 D028 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 14 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 11 Typical Characteristics OP1dB Unless specified all plots ...

Page 15: ...152 150 D045 TA 40qC TA 25qC TA 85qC Frequency MHz NSD dBm Hz 200 600 1000 1400 1800 2200 2600 170 168 166 164 162 160 158 156 154 152 150 D046 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 15 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 12 Typical Characteristics Noise U...

Page 16: ...ency MHz Unadj CF dBm 0 500 1000 1500 2000 2500 3000 3500 4000 4500 70 65 60 55 50 45 40 35 30 D034 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 16 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 13 Typical Characteristics Unadjusted CF Unless specified all plots were creat...

Page 17: ...SBS dBc 0 500 1000 1500 2000 2500 3000 3500 4000 4500 60 55 50 45 40 35 30 25 D222 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 17 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 14 Typical Characteristics Unadjusted SBS Unless specified all plots were created using TRF3722...

Page 18: ...0 500 1000 1500 2000 2500 3000 3500 4000 4500 60 55 50 45 40 35 30 25 20 D201 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 18 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 15 Typical Characteristics LO Harmonic Unless specified all plots were created using TRF3722EVM VCC ...

Page 19: ...ncy MHz HD3 LO dBc 0 500 1000 1500 2000 2500 3000 3500 4000 4500 80 75 70 65 60 55 50 45 40 35 30 25 D204 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 19 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated Typical Characteristics LO Harmonic continued Unless specified all plots w...

Page 20: ... MHz HD2 BB dBc 0 500 1000 1500 2000 2500 3000 3500 4000 4500 80 75 70 65 60 55 50 45 40 D207 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 20 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 16 Typical Characteristics BB Harmonic Unless specified all plots were created using...

Page 21: ...Hz HD3 BB dBc 0 500 1000 1500 2000 2500 3000 3500 4000 4500 90 85 80 75 70 65 60 55 50 D210 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 21 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated Typical Characteristics BB Harmonic continued Unless specified all plots were created us...

Page 22: ...WS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 17 Typical Characteristics RF Output Return Loss Unless specified all plots were created at RFOUT pin using TRF3722EVM VCC 3 3 V VCC_TK 5 V and TA 25 C Figure 74 Smith Chart Figure 75 RFOUT S22 vs Frequency ...

Page 23: ...75 50 25 500 1k 10k 100k 1M 10M 40M D088 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 23 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 18 Typical Characteristics PLL VCO Unless specified all plots were created using TRF3722EVM VCC 3 3 V VCC_TK 5 V and TA 25 C Measured at ...

Page 24: ... MHz Offset Frequency Hz Phase Noise dBc Hz 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 500 1k 10k 100k 1M 10M 40M D095 TA 40qC TA 25qC TA 85qC 24 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated Typical Characteristics PLL VCO continued Unless specified all plots were ...

Page 25: ...3 45V 5 25V Offset Frequency Hz Phase Noise dBc Hz 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 500 1k 10k 100k 1M 10M 40M D101 TA 40qC TA 25qC TA 85qC 25 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated Typical Characteristics PLL VCO continued Unless specified all plot...

Page 26: ...145 140 135 130 125 120 115 110 105 100 95 90 85 80 75 70 D106 TA 40qC TA 25qC TA 85qC Frequency MHz PFD Spur dBc 0 500 1000 1500 2000 2500 3000 3500 4000 4500 150 145 140 135 130 125 120 115 110 105 100 95 90 85 80 75 70 D107 VCC 3 15 4 75 VCC 3 30 5 00 VCC 3 45 5 25 26 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright ...

Page 27: ...00 95 90 85 80 75 70 D111 1 x REF 2 x REF 3 x REF Frequency MHz 3609 6MHz Frac Spur dBc 0 0001 0 001 0 01 0 1 0 2 0 5 1 2 3 5 10 20 20 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 D112 TA 40qC TA 25qC TA 85qC 27 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated Typic...

Page 28: ...0 3000 3500 4000 4500 2 1 0 1 2 3 4 5 6 7 8 D116 TA 40qC TA 25qC TA 85qC 28 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated Typical Characteristics PLL VCO continued Unless specified all plots were created using TRF3722EVM VCC 3 3 V VCC_TK 5 V and TA 25 C Measured at LO_OUTP wit...

Page 29: ...388 396 404 412 420 D228 TA 40qC TA 25qC TA 85qC Frequency MHz I CC mA 0 500 1000 1500 2000 2500 3000 3500 4000 4500 340 348 356 364 372 380 388 396 404 412 420 D229 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 29 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated 6 19 Typical C...

Page 30: ... 8 27 27 2 27 4 27 6 27 8 28 D235 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 30 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated Typical Characteristics Current Consumption continued Figure 116 5V Supply Current vs Temperature Typical Operating Mode Figure 117 5V Supply Curr...

Page 31: ...8 0 9 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 D075 TA 40qC TA 25qC TA 85qC Frequency MHz 3 3V P DISS W 0 500 1000 1500 2000 2500 3000 3500 4000 4500 0 8 0 9 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 D076 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 31 TRF3722 www ti com SLWS245B MAY 2014 REVISED FEBRUARY 2017 Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Inc...

Page 32: ...1 2 1 3 1 4 1 5 1 6 1 7 1 8 D081 TA 40qC TA 25qC TA 85qC Frequency MHz P DISS W 0 500 1000 1500 2000 2500 3000 3500 4000 4500 0 8 0 9 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 D082 VCC 3 15V 4 75V VCC 3 30V 5 00V VCC 3 45V 5 25V 32 TRF3722 SLWS245B MAY 2014 REVISED FEBRUARY 2017 www ti com Product Folder Links TRF3722 Submit Documentation Feedback Copyright 2014 2017 Texas Instruments Incorporated Typical...

Page 33: ... are total of three signals that must be applied the clock CLK the serial data DATA and the latch enable LE The fouth signal is the read back RDBK signal The serial data DB0 DB31 are loaded least significant bit LSB first and read on the rising edge of the CLK LE is asynchronous to the CLK signal at its rising edge the data in the shift register are loaded into the selected internal register Figur...

Page 34: ...k function Each read back is composed by two phases writing followed by the actual reading of the internal data This is shown in the timing diagram in Figure 131 Figure 131 4WI Read Back Timing Diagram During the writing phase a command is sent to TRF3722 register 0 to set it in read back mode and to specify which register is to be read In the proper reading phase at each rising clock edge the int...

Page 35: ...on 8 1 Overview TRF3722 integrates a high performance direct conversion quadrature modulator with exceptional linearity and low noise performance The modulator which upconverts low frequency baseband signal to high frequency RF typically operates at 0 25 V common mode It supports seamless interface with current source DACs It also features high gain and low power operating modes Additionally TRF37...

Page 36: ...on TRF3722 evaluation board though it is possible to modify this value if necessary to match to an external filter load impedance requirement 8 3 3 LO Output The LO outputs are open collector differential outputs and are biased externally These differential outputs can be tuned to optimized output power along with OUTBUF_BIAS register settings It also is possible to use LO outputs in single ended ...

Page 37: ... may be applied If an external LO is used the internal PLL can be powered down Alternatively dividers phase frequency detector and charge pump can remain enabled and may be used to control the VTUNE of an external VCO EN_EXTVCO is used to select the internal or external VCO 8 3 6 Loop Filter Loop filter design is critical for achieving low closed loop phase noise Complete modulator performance dat...

Page 38: ...tector by comparing the two input signals When the two compared phase signals remain aligned for several clock cycles an internal signal goes high The precision of this comparison is controlled through the LD_ANA_PREC bits This internal signal is then averaged and compared against a reference voltage to generate the lock detect LD signal The number of averages used is controlled through LD_DIG_PRE...

Page 39: ...4100 MHz TX_DIV_SEL 1 TX DIV 2 1025 MHz ƒTX 2050 MHz TX_DIV_SEL 2 TX DIV 4 512 5 MHz ƒTX 1025 MHz TX_DIV_SEL 3 TX DIV 8 256 25 MHz ƒTX 512 5 MHz LO_DIV_SEL 0 LO DIV 1 2050 MHz ƒLO 4100 MHz LO_DIV_SEL 1 LO DIV 2 1025 MHz ƒLO 2050 MHz LO_DIV_SEL 2 LO DIV 4 512 5 MHz ƒLO 1025 MHz LO_DIV_SEL 3 LO DIV 8 256 25 MHz ƒLO 512 5 MHz b PLL_DIV_SEL Given fVCO select PLL_DIV_SEL so that the division ratio PLL ...

Page 40: ... the digital divider fN is less than or equal to 375 MHz If fN exceeds 375 MHz choose a larger value for PLL_DIV_SEL and recalculate fPFD RDIV NINT NFRAC and PRSC_SEL 8 4 2 Setup Example for Integer Mode Suppose the following operating characteristics fractional example are desired for Integer mode operation fREF 61 44 MHz reference input frequency Step at RF 2 56 MHz RF channel spacing fRF 1799 6...

Page 41: ...NE is approximately equal to the open loop calibration reference voltage set by VCO_CAL_REF An on chip temperature sensor automatically adjusts this reference voltage so that proper lock can be maintained over the temperature range The calibration logic is driven by a CAL_CLK signal which is scaled version of the reference frequency according to CAL_CLK_SEL For optimum accuracy It is recommended t...

Page 42: ..._TRIM Bit8 PWD_VCO_MUX IB_MOD_LO Bit9 PWD _DIV124 Bit10 PWD_PRESC VCO_BIAS Bit11 RSV Bit12 PWD_OUTBUF Bit13 PWD_LO_DIV EN_LOCKDET Bit14 PWD_TX_DIV VCOBUF_BIAS VCO_TEST_MODE Bit15 PWD_MOD CAL_BYPASS Bit16 EN_EXTVCO VCOMUX_BIAS MUX_CTRL Bit17 RSV Bit18 RSV EN_ISOURCE OUTBUF_BIAS Bit19 REF_INV LD_ANA_PREC ISOURCE_SINKB Bit20 NEG_VCO RSV ISOURCE_TRIM Bit21 ICP PLL_DIV_SEL CP_TRISTATE Bit22 VCO_CAL_IB ...

Page 43: ...DIV 6 0 Bit12 RDIV 7 0 Bit13 RDIV 8 0 Bit14 RDIV 9 0 Bit15 RDIV 10 0 Bit16 RDIV 11 0 Bit17 RDIV 12 0 Bit18 RSV 0 Reserved Bit19 REF_INV 0 Invert Reference Clock Polarity 1 use falling edge Bit20 NEG_VCO 1 VCO polarity control 1 negative slope negative Kv Bit21 ICP 0 0 Program charge pump DC current 00000 1 94 mA 11111 0 47 mA 01010 0 97 mA Bit22 ICP 1 1 Bit23 ICP 2 0 Bit24 ICP 3 1 Bit25 ICP 4 0 Bi...

Page 44: ...0 1 64 0110 2 1101 1 32 0101 4 1100 1 16 0100 8 1011 1 8 0011 16 1010 1 4 0010 32 1001 1 2 0001 64 1000 1 0000 128 ICP 4 0 Set the charge pump current Table 7 Charge Pump Current Set Point ICP 4 0 Current mA ICP 4 0 Current mA 00 000 1 94 10 000 0 75 00 001 1 76 10 001 0 72 00 010 1 62 10 010 0 69 00 011 1 49 10 011 0 67 00 100 1 38 10 100 0 65 00 101 1 29 10 101 0 63 00 110 1 21 10 110 0 61 00 11...

Page 45: ...0 Bit14 NINT 9 0 Bit15 NINT 10 0 Bit16 NINT 11 0 Bit17 NINT 12 0 Bit18 NINT 13 0 Bit19 NINT 14 0 Bit20 NINT 15 0 Bit21 PLL_DIV_SEL 0 1 Select division ratio of divider in front of prescaler 00 1X 01 div2 10 div4 Bit22 PLL_DIV_SEL 1 0 Bit23 PRSC_SEL 1 Select precaler modulus 0 4 5 1 8 9 Bit24 RSV 0 Reserved Bit25 RSV 0 Bit26 VCO_SEL 0 0 Selects between the four integrated VCOs 00 lowest frequency 1...

Page 46: ... Bit4 ADDR 4 0 Bit5 NFRAC 0 0 Fractional PLL N Divider 0 to 0 99999 in fractional mode Bit6 NFRAC 1 0 Bit7 NFRAC 2 0 Bit8 NFRAC 3 0 Bit9 NFRAC 4 0 Bit10 NFRAC 5 0 Bit11 NFRAC 6 0 Bit12 NFRAC 7 0 Bit13 NFRAC 8 0 Bit14 NFRAC 9 0 Bit15 NFRAC 10 0 Bit16 NFRAC 11 0 Bit17 NFRAC 12 0 Bit18 NFRAC 13 0 Bit19 NFRAC 14 0 Bit20 NFRAC 15 0 Bit21 NFRAC 16 0 Bit22 NFRAC 17 0 Bit23 NFRAC 18 0 Bit24 NFRAC 19 0 Bit...

Page 47: ... Power down TX divider block 1 off Bit15 PWD_MOD 1 Power down modulator block 1 off Bit16 EN_EXTVCO 0 Enable external VCO input buffer 1 enabled Bit17 RSV 0 Reserved Bit18 EN_ISOURCE 0 Enable offset current at CP output frac n mode only Bit19 LD_ANA_PREC 0 0 Control precision of Analog Lock Detector 00 H H High 01 L L Low 10 H L 11 L L Bit20 LD_ANA_PREC 1 0 Bit21 CP_TRISTATE 0 0 Set the charge pum...

Page 48: ...F_BIAS 0 0 Adjust VCO buffer reference current Bit15 VCOBUF_BIAS 1 1 Bit16 VCOMUX_BIAS 0 0 Adjust VCO Mux reference current Bit17 VCOMUX_BIAS 1 1 Bit18 OUTBUF_BIAS 0 0 Adjust output buffer current Bit19 OUTBUF_BIAS 1 1 Bit20 RSV 0 Reserved Bit21 RSV 1 Bit22 VCO_CAL_IB 0 Bias current for CAL reference voltage 0 PTAT 1 Constant Bit23 VCO_CAL_REF 0 0 VCO calibration reference voltage adjustment 000 0...

Page 49: ...ach VCO Bit15 CAL_BYPASS 0 Bypass auto cal sets VCO_SEL and VCO_TRIM from Serial interface Bit16 MUX_CTRL 0 1 Select signal for test output 001 LD 010 NDIV 100 RDIV 110 A_counter Bit17 MUX_CTRL 1 0 Bit18 MUX_CTRL 2 0 Bit19 ISOURCE_SINKB 0 Offset current polarity Bit20 ISOURCE_TRIM 0 0 Adjust Isource bias current in frac n mode Bit21 ISOURCE_TRIM 1 0 Bit22 ISOURCE_TRIM 2 1 Bit23 LO_DIV_SEL 0 0 Adju...

Page 50: ... Table 13 READBACK Mode Summary Serial interface Map Bit Register 0 RDBK Bit0 Register Address Register Address Bit1 Bit2 Bit3 Bit4 Bit5 CHIP_ID N C Bit6 Bit7 NU Bit8 Bit9 Bit10 Bit11 Bit12 R_SAT_ERR Bit13 COUNT VCO_TRIM Bit14 Bit15 Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 VCO_SEL Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 MUX_COUNT Bit28 RB_REG Bit29 Bit30 Bit31 MUX_COUNT RB_ENABLE ...

Page 51: ...div saturation error for cal Bit13 COUNT 0 NU x VCO frequency counter high when MUX_COUNT 0 and VCO_TEST_MODE 1 VCO frequency counter low when MUX_COUNT 1 and VCO_TEST_MODE 1 Autocal results for VCO_TRIM and VCO_SEL when VCO_TEST_MODE 0 Bit14 COUNT 1 NU x Bit15 COUNT 2 VCO_TRIM 0 x Bit16 COUNT 3 VCO_TRIM 1 x Bit17 COUNT 4 VCO_TRIM 2 x Bit18 COUNT 5 VCO_TRIM 3 x Bit19 COUNT 6 VCO_TRIM 4 x Bit20 COU...

Page 52: ...it3 ADDR 3 1 Bit4 ADDR 4 0 Bit5 N C 0 Bit6 N C 0 Bit7 N C 0 Bit8 N C 0 Bit9 N C 0 Bit10 N C 0 Bit11 N C 0 Bit12 N C 0 Bit13 N C 0 Bit14 N C 0 Bit15 N C 0 Bit16 N C 0 Bit17 N C 0 Bit18 N C 0 Bit19 N C 0 Bit20 N C 0 Bit21 N C 0 Bit22 N C 0 Bit23 N C 0 Bit24 N C 0 Bit25 N C 0 Bit26 N C 0 Bit27 MUX_COUNT 0 0 max freq count 1 min freq count Bit28 RB_REG 0 x Three LSBs of the address for the register th...

Page 53: ... x x x REGISTER 2 CAL_ACC 0 0 0 0 0 REGISTER 2 EN_CAL 1 1 1 1 1 REGISTER 3 NFRAC 0 0 0 0 x REGISTER 4 PWD_PLL 0 0 0 0 0 REGISTER 4 PWD_CP 0 0 0 0 0 REGISTER 4 PWD_VCO 0 0 0 0 0 REGISTER 4 PWD_VCO_MUX 0 0 0 0 0 REGISTER 4 PWD _DIV124 0 0 0 0 0 REGISTER 4 PWD_PRESC 0 0 0 0 0 REGISTER 4 PWD_OUTBUF 0 0 0 1 0 REGISTER 4 PWD_LO_DIV 0 0 0 1 0 REGISTER 4 PWD_TX_DIV 0 0 0 0 0 REGISTER 4 PWD_MOD 0 0 0 0 0 R...

Page 54: ...T MODE TYPICAL OPERATING MODE 2GHz 3GHz INT MODE TYPICAL OPERATING MODE 3GHz 4 1GHz INT MODE LOW POWER MODE INT MODE FRACTIONAL MODE REGISTER 6 VCO_TRIM x x x x x REGISTER 6 EN_LOCKDET 0 0 0 0 0 REGISTER 6 VCO_TEST_MODE 0 0 0 0 0 REGISTER 6 CAL_BYPASS 0 0 0 0 0 REGISTER 6 MUX_CTRL 1 1 1 1 5 REGISTER 6 ISOURCE_SINKB 0 0 0 0 0 REGISTER 6 ISOURCE_TRIM 4 4 4 4 7 REGISTER 6 LO_DIV_SEL x x x x x REGISTE...

Page 55: ...15 VCC_MOD2 16 GND 17 RFOUT 18 GND 19 GND 20 VCC_MOD3 21 GND 22 VCC_MOD4 23 NC4 24 NC5 25 GND 26 BBI_P 27 NC6 28 BBI_N 29 GND 30 EXT_VCO 31 VCC_TK 32 VCC_VCO 33 VTUNE 34 VCC_LO2 35 NC7 36 GND 37 LO_OUTN 38 LO_OUTP 39 GND 40 PWRPAD 49 CP_OUT 41 VCC_PLL 42 GND 43 REFIN 44 GND 45 LE 46 DATA 47 CLK 48 1K FB22 1K FB16 C29 4 7pF C28 4 7pF R22 49 9 C55 4 7pF 55 TRF3722 www ti com SLWS245B MAY 2014 REVISE...

Page 56: ...l output as configured by MUX_CTRL 8 10 27 29 BBI_P BBI_N BBQ_P BBQ_N In phase and quadrature baseband differential baseband signals Typical 0 25V common mode is needed 18 RFOUT Modulator RF output must be ac coupled and can drive 50 Ω load 31 EXT_VCO External local oscillator input high impedance normally ac coupled If unused terminate to 50 ohms load 38 39 LO_OUTP LO_OUTN Local oscillator output...

Page 57: ...ltage of the DAC can be translated to the proper common mode voltage of the modulator The TRF3722 common mode voltage is typically 0 25 V and is ideally suited to interface with the DAC3482 3484 DAC348x and DAC38J8x family The interface network is shown in Figure 136 Figure 136 DAC348x Interface with the TRF3722 Modulator The DAC348x requires a load resistance of 25 Ω per branch to maintain its op...

Page 58: ...MHz RF 1842 5 MHz Figure 137 152 9 MHz IF DAC34H84 TRF3722 20 MHz LTE ACPR Figure 138 152 9 MHz IF 6 Carrier MC GSM DAC34H84 TRF3722 ACPR Performance 10 Power Supply Recommendations The TRF3722 is powered by supplying a nominal 3 3 V and 5 V It can also be powered using only 3 3V supply Proper RF bypassing should be placed close to each power supply pin Ground pin connections should have at least ...

Page 59: ...ack Copyright 2014 2017 Texas Instruments Incorporated 11 Layout 11 1 Layout Guidelines Layout of the application board significantly impacts the analog performance of the TRF3722 device Noise and high speed signals should be prevented from leaking onto power supply terminals or analog signals The TRF3722 device is fitted with a ground slug on the back of the package that must be soldered to the p...

Page 60: ...esign Support TI s Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support 12 3 Trademarks PowerPAD E2E are trademarks of Texas Instruments All other trademarks are the property of their respective owners 12 4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD Texas Instruments recommends that all integ...

Page 61: ...f 1000ppm threshold Antimony trioxide based flame retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature 4 There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device 5 Multiple Devic...

Page 62: ...PACKAGE OPTION ADDENDUM www ti com 10 Dec 2020 Addendum Page 2 ...

Page 63: ...Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant TRF3722IRGZR VQFN RGZ 48 2500 330 0 16 4 7 3 7 3 1 5 12 0 16 0 Q2 TRF3722IRGZT VQFN RGZ 48 250 180 0 16 4 7 3 7 3 1 5 12 0 16 0 Q2 PACKAGE MATERIALS INFORMATION www ti com 12 Feb 2019 Pack Materials Page 1 ...

Page 64: ... Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TRF3722IRGZR VQFN RGZ 48 2500 350 0 350 0 43 0 TRF3722IRGZT VQFN RGZ 48 250 213 0 191 0 55 0 PACKAGE MATERIALS INFORMATION www ti com 12 Feb 2019 Pack Materials Page 2 ...

Page 65: ...VIEW Images above are just a representation of the package family actual package may vary Refer to the product data sheet for package details VQFN 1 mm max height RGZ 48 PLASTIC QUADFLAT PACK NO LEAD 7 x 7 0 5 mm pitch 4224671 A ...

Page 66: ...al thermal and mechanical performance PACKAGE OUTLINE 4219044 C 09 2020 www ti com VQFN 1 mm max height PLASTIC QUADFLAT PACK NO LEAD RGZ0048A A 0 08 C 0 1 C A B 0 05 C B SYMM SYMM PIN 1 INDEX AREA 7 1 6 9 7 1 6 9 1 MAX 0 05 0 00 SEATING PLANE C 5 15 0 1 2X 5 5 2X 5 5 44X 0 5 48X 0 5 0 3 48X 0 30 0 18 PIN1 ID OPTIONAL 0 2 TYP 1 12 13 24 25 36 37 48 0 1 TYP SIDE WALL DETAIL OPTIONAL METAL THICKNESS...

Page 67: ...vias under paste be filled plugged or tented EXAMPLE BOARD LAYOUT 4219044 C 09 2020 www ti com VQFN 1 mm max height RGZ0048A PLASTIC QUADFLAT PACK NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE 15X 5 15 2X 6 8 2X 6 8 48X 0 6 48X 0 24 44X 0 5 2X 5 5 2X 5 5 21X Ø0 2 VIA TYP R0 05 TYP NON SOLDER MASK DEFINED PREFERRED SOLDER MASK DEFINED METAL SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DETAILS SOLDE...

Page 68: ...esign recommendations EXAMPLE STENCIL DESIGN 4219044 C 09 2020 www ti com VQFN 1 mm max height RGZ0048A PLASTIC QUADFLAT PACK NO LEAD SOLDER PASTE EXAMPLE BASED ON 0 125 mm THICK STENCIL EXPOSED PAD 67 PRINTED COVERAGE BY AREA SCALE 15X SYMM SYMM 1 06 2X 6 8 2X 6 8 48X 0 6 48X 0 24 44X 0 5 2X 5 5 2X 5 5 R0 05 TYP 2X 0 63 2X 0 63 2X 1 26 2X 1 26 ...

Page 69: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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