NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
EXAMPLE BOARD LAYOUT
4219044/C 09/2020
www.ti.com
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE: 15X
( 5.15)
2X (6.8)
2X
(6.8)
48X (0.6)
48X (0.24)
44X (0.5)
2X (5.5)
2X
(5.5)
21X (Ø0.2) VIA
TYP
(R0.05)
TYP
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
2X
(1.26)
2X (1.26)
2X (1.065)
2X
(1.065)
1
12
13
22
23
34
35
48