DC Blocking
Capacitor
RF Out
Capacitor
REFIN
RF Out
VCC
Note: Ensure good RF microstrip or stripline
traces are used to connect the external
components to the REFIN, RF and LO output pins
Notes:
1.Ensure all components are connected to a
common RF/DC ground plane with plenty of vias
2. Ensure a low impedance VCC plane is
connected to all VCC terminals
G
N
D
L
D
VC
C
_
D
IG
VC
C
_
L
O
1
G
N
D
N
C
BBQ
_
P
BBQ
_
N
VCC_MOD1
VCC_MOD2
RFOUT
VCC_MOD3
VCC_MOD4
VC
C
_
T
K
VT
U
N
E
N
C
BBI
_
P
N
C
G
N
D
G
N
D
GND
GND
GND
GND
G
N
D
PD
R
D
BK
N
C
NC
GND
NC
N
C
EXT
_
VC
O
VC
C
_
L
O2
VC
C
_
VC
O
BBI
_
N
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
44
45
46
47
48
39
40
41
42
43
37
38
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
DATA
GND
CP_OUT
VCC_PLL
LO_OUTP
GND
CLK
LO_OUTN
REFIN
LE
GND
GND
25
14
13
15
19
18
16
17
20
21
22
23
24
RF &DC
Bypass
Capacitors
RF &DC
Bypass
Capacitors
Baseband
Terminations
Baseband
Terminations
RF &DC
Bypass
Capacitors
PLL Loop
Filter
RF &DC
Bypass
Capacitors
VCC
VCC
VCC
VCC
VCC
LO Out
59
SLWS245B – MAY 2014 – REVISED FEBRUARY 2017
Product Folder Links:
Copyright © 2014–2017, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
Layout of the application board significantly impacts the analog performance of the TRF3722 device. Noise and
high-speed signals should be prevented from leaking onto power-supply terminals or analog signals. The
TRF3722 device is fitted with a ground slug on the back of the package that must be soldered to the printed
circuit board (PCB) ground with adequate ground vias to ensure a good thermal and electrical connection. The
ground pins of the device can be directly tied to the ground slug pad for a low-inductance path to ground.
Additional ground vias may be added if space allows. Follow these recommendations:
•
Place supply decoupling capacitors physically close to the device, on the same side of the board. Isolate
supply terminals with a ferrite bead.
•
Maintain a continuous ground plane in the vicinity of the device and as return paths for all high-speed signal
lines. Place reference plane vias or decoupling capacitors near any signal line reference transition.
•
Power planes should not overlap each other or high-speed signal lines.
•
Isolate REFIN routing from loop filter lines, control lines, and other high-speed lines.
11.2 Layout Example
Figure 139. Layout