C4
330pF
R4
1.1K
C3
330pF
R3
1.1K
R2
1.1K
C2
10nF
C1
1nF
CP_OUT
VTUNE
38
SLWS245B – MAY 2014 – REVISED FEBRUARY 2017
Product Folder Links:
Copyright © 2014–2017, Texas Instruments Incorporated
Feature Description (continued)
Frac-N performance data is obtained using the fractional loop filter shown in
. 40 kHz loop bandwidth
and 15.36 MHz PFD was considered.
Figure 134. Fractional Loop Filter
8.3.7 Lock Detect
The lock detect signal is generated in the phase frequency detector by comparing the two input signals. When
the two compared phase signals remain aligned for several clock cycles, an internal signal goes high. The
precision of this comparison is controlled through the LD_ANA_PREC bits. This internal signal is then averaged
and compared against a reference voltage to generate the lock detect (LD) signal. The number of averages used
is controlled through LD_DIG_PREC. Therefore, when the VCO is frequency locked, LD is high. When the VCO
frequency is not locked, LD may pulse high or exhibit periodic behavior.
By default, the internal lock detect signal is made available on the LD terminal. Register bits MUX_CTRL can be
used to control a multiplexer to output other diagnostic signals on the LD output.