0.1
µF
0.01
µF
50R
1.14V - 1.32V
50R
V
SS
PLL0_VDDA
PLL0_VSSA
Ferrite Bead: Murata BLM31PG500SN1L or Equivalent
OMAP-L137
www.ti.com
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
6.6
Clock PLLs
The OMAP-L137 has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
•
Glitch-Free Transitions (on changing clock settings)
•
Domain Clocks Alignment
•
Clock Gating
•
PLL power down
The various clock outputs given by the controller are as follows:
•
Domain Clocks: SYSCLK [1:n]
•
Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
•
Post-PLL Divider: POSTDIV
•
SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
•
PLL Multiplier Control: PLLM
•
Software programmable PLL Bypass: PLLEN
6.6.1
PLL Device-Specific Information
The OMAP-L137 DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The PLL requires some external filtering components to reduce power supply noise as shown in
Figure 6-
8
.
Figure 6-8. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
OSCIN pin. The PLL outputs seven clocks that have programmable divider options.
Figure 6-9
illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in
Table 6-4
before enabling the DSP to run from the PLL by setting
PLLEN = 1.
Copyright © 2008–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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