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OMAP-L137

SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014

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6.21.2 LCD Raster Mode

Table 6-86. LCD Raster Mode Timing

See

Figure 6-55

through

Figure 6-59

No.

PARAMETER

MIN

MAX

UNIT

1

t

c(PIXEL_CLK)

Cycle time, pixel clock

26.6

ns

2

t

w(PIXEL_CLK_H)

Pulse duration, pixel clock high

10

ns

3

t

w(PIXEL_CLK_L)

Pulse duration, pixel clock low

10

ns

4

t

d(LCD_D_V)

Delay time, LCD_PCLK high to LCD_D[15:0] valid (write)

-0.5

9

ns

5

t

d(LCD_D_IV)

Delay time, LCD_PCLK high to LCD_D[15:0] invalid (write)

-0.5

9

ns

6

t

d(

LCD_AC_ENB_CS_A

)

Delay time, LCD_PCLK low to LCD_AC_ENB_CS high

S2 - 0.5

(1)

S2 + 9

(1)

ns

7

t

d(

LCD_AC_ENB_CS_I)

Delay time, LCD_PCLK low to LCD_AC_ENB_CS low

S2 - 0.5

(1)

S2 + 9

(1)

ns

8

t

d(LCD_VSYNC_A)

Delay time, LCD_PCLK low to LCD_VSYNC high

(2)

-0.5

12

ns

9

t

d(LCD_VSYNC_I)

Delay time, LCD_PCLK low to LCD_VSYNC low

(2)

-0.5

12

ns

10

t

d(LCD_HSYNC_A)

Delay time, LCD_PCLK high to LCD_HSYNC high

(2)

-0.5

12

ns

11

t

d(LCD_HSYNC_I)

Delay time, LCD_PCLK high to LCD_HSYNC low

(2)

-0.5

12

ns

(1)

S2 = SYSCLK2 cycle time in ns

(2)

The activation edge of the control signals LCD_VSYNC and LCD_HSYNC may be programmed to either the rising or falling edge of the
pixel clock through the LCD (RASTER_TIMING_2) register. In

Figure 6-56

through

Figure 6-59

, all signal polarity and activation edges

are based on the default LCD (RASTER_TIMING_2) register settings.

Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:

•

Vertical front porch (VFP)

•

Vertical sync pulse width (VSW)

•

Vertical back porch (VBP)

•

Lines per panel (LPP)

Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:

•

Horizontal front porch (HFP)

•

Horizontal sync pulse width (HSW)

•

Horizontal back porch (HBP)

•

Pixels per panel (PPL)

.

LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)

register:

•

AC bias frequency (ACB)

The display format produced in raster mode is shown in

Figure 6-55

. An entire frame is delivered one line

at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.

166

Peripheral Information and Electrical Specifications

Copyright © 2008–2014, Texas Instruments Incorporated

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Summary of Contents for OMAP-L137 EVM

Page 1: ...x Protected Mode Operation Byte Addressable 8 16 32 and 64 Bit Data Exceptions Support for Error Detection and 8 Bit Overflow Protection Program Redirection Bit Field Extract Set Clear 128KB of RAM Shared Memory Normalization Saturation Bit Counting 3 3 V LVCMOS I Os Except for USB Interfaces Compact 16 Bit Instructions Two External Memory Interfaces C674x Two Level Cache Memory Architecture EMIFA...

Page 2: ...p to Four Event Time End Point 0 Control Stamps End Points 1 2 3 4 Control Bulk Interrupt or Two 32 Bit Enhanced Quadrature Encoder Pulse ISOC RX and TX eQEP Modules Three Multichannel Audio Serial Ports McASPs 256 Ball Pb Free Plastic Ball Grid Array PBGA Six Clock Zones and 28 Serial Data Pins ZKB Suffix 1 0 mm Ball Pitch Supports TDM I2S and Similar Formats Commercial Industrial Extended or Aut...

Page 3: ... resolution pulse width modulator eHRPWM peripherals three 32 bit enhanced capture eCAP module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator APWM outputs two 32 bit enhanced quadrature encoded pulse eQEP peripherals and 2 external memory interfaces an asynchronous and SDRAM external memory interface EMIFA for slower memories or peripherals and a highe...

Page 4: ... 3 DMA Peripherals Display Internal Memory LCD Ctlr 128KB RAM External Memory Interfaces Connectivity EDMA3 Control Timers eHRPWM 3 eCAP 3 eQEP 2 10 100 EMAC RMII MDIO USB1 1 OHCI Ctlr PHY USB2 0 OTG Ctlr PHY HPI MMC SD 8b EMIFA 8b 16B NAND Flash 16b SDRAM EMIFB SDRAM Only 16b 32b GPIO PRU Subsystem OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com 1 4 Functional Block Diagram Note No...

Page 5: ...Controller Registers USB1 1 OHCI 181 5 Device Operating Conditions 52 6 26 USB0 OTG USB2 0 OTG 182 5 1 Absolute Maximum Ratings Over Operating Case Temperature Range 6 27 Host Port Interface UHPI 190 Unless Otherwise Noted 52 6 28 Power and Sleep Controller PSC 197 5 2 Handling Ratings 52 6 29 Programmable Real Time Unit Subsystem 5 3 Recommended Operating Conditions 53 PRUSS 200 5 4 Notes on Reco...

Page 6: ...ion 3 7 Updated Changed USB0_VDDA12 DESCRIPTION from must always be connected via a 1 μF Terminal Functions capacitor to is recommended to be connected via a 0 22 μF capacitor Section 3 7 11 Universal Table 3 15 Universal Asynchronous Receiver Transmitter UART Terminal Functions Asynchronous Updated Changed footnote from Applications Processor System Reference Guide Literature Number Receiver Tran...

Page 7: ...ning range rated devices for 400 375 300 266 200 MHz max CPU Data Timing operating Updated Changed CVDD 1 3V MIN column values for Parameter No 4 6 8 10 12 14 16 and 18 from 0 9 to 1 1 Updated Changed CVDD 1 3V MAX column values for Parameter No 3 5 7 9 11 13 15 and 17 from 5 1 to 4 25 Populated CVDD 1 2V column with values was empty Updated Changed Parameter No 18 from tena CLKH DLZ to t CLKH DLZ...

Page 8: ...erface same time for more I O detail see the Device Configurations section eHRPWM 6 Single Edge 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs eCAP 3 32 bit capture inputs or 3 32 bit auxiliary PWM outputs eQEP 2 32 bit QEP channels with 4 inputs channel UHPI 1 16 bit multiplexed address data USB 2 0 USB0 High Speed OTG Controller with on chip OTG PHY USB 1 1 USB1 Full Speed OHCI as host ...

Page 9: ...ion cache 16KB Data cache Write Buffer Embedded Trace Module and Embedded Trace Buffer ETM ETB ARM Interrupt controller 3 3 1 ARM926EJ S RISC CPU The ARM Subsystem integrates the ARM926EJ S processor The ARM926EJ S processor is a member of ARM9 family of general purpose microprocessors This processor is targeted at multi tasking applications where full memory management high performance low die si...

Page 10: ...e table walks Invalidate entire TLB using CP15 register 8 Invalidate TLB entry selected by MVA using CP15 register 8 Lockdown of TLB entries using CP15 register 10 3 3 4 Caches and Write Buffer The size of the Instruction cache is 16KB Data cache is 16KB Additionally the caches have the following features Virtual index virtual tag and addressed using the Modified Virtual Address MVA Four way set a...

Page 11: ...mparators counter and sequencers The OMAP L137 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer The ETB has a 4KB buffer memory ETB enabled debug tools are required to read interpret the captured trace data This device uses ETM9 version r2p2 and ETB version r0p1 Documentation on the ETM and ETB is available from ARM Ltd Reference the CoreSight ETM9 Technical ...

Page 12: ...DMA 256 256 256 256 256 64 High Performance Switch Fabric 64 64 64 Configuration Peripherals Bus 32 OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com 3 4 DSP Subsystem The DSP Subsystem includes the following features C674x DSP CPU 32KB L1 Program L1P Cache up to 32KB 32KB L1 Data L1D Cache up to 32KB 256KB Unified Mapped RAM Cache L2 Boot ROM cannot be used for application code Littl...

Page 13: ...ty of signed and unsigned 32 bit data types The L Unit or Arithmetic Logic Unit now incorporates the ability to do parallel add subtract operations on a pair of common inputs Versions of this instruction exist to work on 32 bit data or on pairs of 16 bit data performing dual 16 bit add and subtracts in parallel There are also saturated forms of these instructions The C674x core enhances the S unit...

Page 14: ... in the CPU which is not sensitive to system stalls For more details on the C674x CPU and its enhancements over the C64x architecture see the following documents TMS320C64x C64x DSP CPU and Instruction Set Reference Guide SPRU732 TMS320C64x Technical Overview SPRU395 14 Device Overview Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 15: ... dst Á Á Á src1 Data path B Control Register 32 MSB 32 LSB dst2 A 32 MSB 32 LSB 2x 1x 32 LSB 32 MSB 32 LSB 32 MSB dst2 B B A 8 8 8 8 32 32 32 32 C C Even register file A A0 A2 A4 A30 Even register file B B0 B2 B4 B30 D D D D A On M unit dst2 is 32 MSB B On M unit dst1 is 32 LSB C On C64x CPU M unit src2 is 32 bits on C64x CPU M unit src2 is 64 bits D On L and S units odd dst connects to odd regist...

Page 16: ...tween program and data space L2 memory can be configured as mapped memory cache or a combination of both Table 3 2 shows a memory map of the C674x CPU cache registers for the device Table 3 2 C674x Cache Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION L2 Cache configuration register See the Technical Reference Manual 0x0184 0000 L2CFG SPRUH92 for the reset configuration L1P Size Cache configur...

Page 17: ...AR63 Reserved 0x0000 0000 0x3FFF FFFF Memory Attribute Registers for EMIFA SDRAM Data CS0 0x0184 8100 0x0184 817F MAR64 MAR95 0x4000 0000 0x5FFF FFFF Memory Attribute Registers for EMIFA Async Data CS2 0x0184 8180 0x0184 8187 MAR96 MAR97 0x6000 0000 0x61FF FFFF Memory Attribute Registers for EMIFA Async Data CS3 0x0184 8188 0x0184 818F MAR98 MAR99 0x6200 0000 0x63FF FFFF Memory Attribute Registers...

Page 18: ...PA9 controls memory address 0x0081 2000 0x0081 3FFF L2 memory protection page attribute register 10 0x0184 A228 L2MPPA10 controls memory address 0x0081 4000 0x0081 5FFF L2 memory protection page attribute register 11 0x0184 A22C L2MPPA11 controls memory address 0x0081 6000 0x0081 7FFF L2 memory protection page attribute register 12 0x0184 A230 L2MPPA12 controls memory address 0x0081 8000 0x0081 9F...

Page 19: ... L2 memory protection page attribute register 37 0x0184 A294 L2MPPA37 controls memory address 0x0072 8000 0x0072 FFFF L2 memory protection page attribute register 38 0x0184 A298 L2MPPA38 controls memory address 0x0073 0000 0x0073 7FFF L2 memory protection page attribute register 39 0x0184 A29C L2MPPA39 controls memory address 0x0073 8000 0x0073 FFFF L2 memory protection page attribute register 40 ...

Page 20: ...FAR L1P memory protection fault address register 0x0184 A404 L1PMPFSR L1P memory protection fault status register 0x0184 A408 L1PMPFCR L1P memory protection fault command register 0x0184 A40C 0x0184 A4FF Reserved 0x0184 A500 L1PMPLK0 L1P memory protection lock key bits 31 0 0x0184 A504 L1PMPLK1 L1P memory protection lock key bits 63 32 0x0184 A508 L1PMPLK2 L1P memory protection lock key bits 95 64...

Page 21: ...AD08 L1DMPLK2 L1D memory protection lock key bits 95 64 0x0184 AD0C L1DMPLK3 L1D memory protection lock key bits 127 96 0x0184 AD10 L1DMPLKCMD L1D memory protection lock key command register 0x0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register 0x0184 AD18 0x0184 ADFF Reserved 0x0184 AE00 0x0184 AE3F Reserved 2 L1D memory protection page attribute register 16 0x0184 AE40 L1DMPPA16...

Page 22: ...PPA28 controls memory address 0x00F0 6000 0x00F0 67FF L1D memory protection page attribute register 29 0x0184 AE74 L1DMPPA29 controls memory address 0x00F0 6800 0x00F0 6FFF L1D memory protection page attribute register 30 0x0184 AE78 L1DMPPA30 controls memory address 0x00F0 7000 0x00F0 77FF L1D memory protection page attribute register 31 0x0184 AE7C L1DMPPA31 controls memory address 0x00F0 7800 0...

Page 23: ... ID 0x0181 3000 0x0181 FFFF 52K 0x0182 0000 0x0182 FFFF 64K DSP EMC 0x0183 0000 0x0183 FFFF 64K DSP Internal Reserved 0x0184 0000 0x0184 FFFF 64K DSP Memory System 0x0185 0000 0x01BB FFFF 0x01BC 0000 0x01BC 0FFF 4K ARM ETB memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB reg 0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller 0x01C0 800...

Page 24: ... 0x01D0 B000 0x01D0 BFFF 0x01D0 C000 0x01D0 CFFF 4K UART 1 0x01D0 D000 0x01D0 DFFF 4K UART 2 0x01D0 E000 0x01DF FFFF 0x01E0 0000 0x01E0 FFFF 64K USB0 0x01E1 0000 0x01E1 0FFF 4K UHPI 0x01E1 1000 0x01E1 1FFF 0x01E1 2000 0x01E1 2FFF 4K SPI 1 0x01E1 3000 0x01E1 3FFF 4K LCD Controller 0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 MPU 1 0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 MPU 2 0x0...

Page 25: ...00 0x5FFF FFFF 0x6000 0000 0x61FF FFFF 32M EMIFA async data CS2 0x6200 0000 0x63FF FFFF 32M EMIFA async data CS3 0x6400 0000 0x65FF FFFF 32M EMIFA async data CS4 0x6600 0000 0x67FF FFFF 32M EMIFA async data CS5 0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers 0x6800 8000 0x7FFF FFFF 0x8000 0000 0x8001 FFFF 128K Shared RAM 0x8002 0000 0xAFFF FFFF 0xB000 0000 0xB000 7FFF 32K EMIFB Control Registe...

Page 26: ...PWM0A GP3 15 AFSX1 EPWMSYNCI EPWMSYNCO GP4 10 DVDD CVDD VSS VSS CVDD CVDD DVDD EMB_D 20 EMB_WE_ DQM 0 GP5 15 EMB_WE EMB_D 21 CVDD TMS J TDI TDO TRST EMU0 GP7 15 CVDD CVDD VSS VSS CVDD CVDD CVDD EMB_D 5 GP6 5 EMB_D 19 EMB_D 6 GP6 6 EMB_D 7 GP6 7 RTC_XI H RTC_XO TCK NC USB0_ VDDA33 CVDD VSS VSS CVDD CVDD EMB_D 3 GP6 3 EMB_D 17 EMB_D 18 EMB_D 4 GP6 4 RTC_CVDD G RTC_VSS RESET USB0_DM DVDD CVDD VSS VSS...

Page 27: ...Ground A Analog signal Note For multiplexed pins where functions have different types ie input versus output the table reflects the pin function direction for that particular peripheral 2 IPD Internal Pulldown resistor IPU Internal Pullup resistor 3 Open drain mode for RESETOUT function 3 7 2 High Frequency Oscillator and PLL Table 3 6 High Frequency Oscillator and PLL Terminal Functions PIN NO SI...

Page 28: ... I O IPD EMA_D 10 UHPI_HD 10 LCD_D 10 GP0 10 R14 I O IPD EMA_D 9 UHPI_HD 9 LCD_D 9 GP0 9 T14 I O IPD EMA_D 8 UHPI_HD 8 LCD_D 8 GP0 8 N12 I O IPD MMC SD UHPI EMIFA data bus EMA_D 7 MMCSD_DAT 7 UHPI_HD 7 GP0 7 BOOT 13 M15 I O IPU GPIO BOOT EMA_D 6 MMCSD_DAT 6 UHPI_HD 6 GP0 6 N13 I O IPU EMA_D 5 MMCSD_DAT 5 UHPI_HD 5 GP0 5 N15 I O IPU EMA_D 4 MMCSD_DAT 4 UHPI_HD 4 GP0 4 P13 I O IPU MMC SD UHPI GPIO E...

Page 29: ...2 O IPU EMIFA clock OBSCLK EMIFA SDRAM clock EMA_SDCKE GP2 0 T12 O IPU GPIO enable EMIFA SDRAM row EMA_RAS EMA_CS 5 GP2 2 N7 O IPU address strobe EMIF A chip select GPIO EMIFA SDRAM column EMA_CAS EMA_CS 4 GP2 1 L16 O IPU address strobe EMA_RAS EMA_CS 5 GP2 2 N7 O IPU EMIF A SDRAM GPIO EMA_CAS EMA_CS 4 GP2 1 L16 O IPU EMIFA Async Chip EMA_CS 3 AMUTE2 GP2 6 T7 O IPU McASP2 GPIO Select UHPI GPIO EMA...

Page 30: ... I O IPD EMB_D 2 GP6 2 G16 I O IPD EMB_D 1 GP6 1 G13 I O IPD EMB_D 0 GP6 0 F16 I O IPD EMB_A 12 GP3 13 B15 O IPD EMB_A 11 GP7 13 B12 O IPD EMB_A 10 GP7 12 A9 O IPD EMB_A 9 GP7 11 C12 O IPD EMIFB SDRAM row column GPIO address bus EMB_A 8 GP7 10 D12 O IPD EMB_A 7 GP7 9 A11 O IPD EMB_A 6 GP7 8 B11 O IPD EMB_A 5 GP7 7 C11 O IPD 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage G...

Page 31: ... SDRAM bank address EMB_BA 0 GP7 1 C9 O IPU EMB_CLK C14 O IPU EMIF SDRAM clock EMB_SDCKE C13 O IPU EMIFB SDRAM clock enable EMB_WE K15 O IPU EMIFB write enable EMIFB SDRAM row address EMB_RAS A8 O IPU strobe EMB_CAS L13 O IPU EMIFB column address strobe EMB_CS 0 D9 O IPU EMIFB SDRAM chip select 0 EMB_WE_DQM 3 A12 O IPU EMB_WE_DQM 2 B13 O IPU EMIFB write enable data mask for EMB_D EMB_WE_DQM 1 GP5 ...

Page 32: ...IPD eQEP1 GPIO BOOT SPI1 clock SPI1 data slave in SPI1_SIMO 0 I2C1_SDA GP5 6 BOOT 6 N5 I O IPU master out I2C1 GPIO BOOT SPI1 data slave out SPI1_SOMI 0 I2C1_SCL GP5 5 BOOT 5 P5 I O IPU master in 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A Analog signal Note The pin type shown refers to the input output or high impedance state of the pin function when conf...

Page 33: ... McASP1 GPIO input or auxiliary PWM 2 output 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A Analog signal Note The pin type shown refers to the input output or high impedance state of the pin function when configured as the the signal name highlighted in bold All multiplexed signals may enter a high impedance state when the configured function is input only o...

Page 34: ...WM2 eHRPWM2 A output AXR1 6 EPWM2A GP4 6 M4 I O IPD with high resolution McASP1 GPIO AXR1 5 EPWM2B GP4 5 N1 I O IPD eHRPWM2 B output McASP1 eHRPWM1 eHRPWM2 trip zone AMUTE1 EPWMTZ GP4 14 D4 I O IPD GPIO eHRPWM2 input 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A Analog signal Note The pin type shown refers to the input output or high impedance state of the p...

Page 35: ...PD SPI0 GPIO BOOT eQEP1 index SPI1_CLK EQEP1S GP5 7 BOOT 7 T6 I IPD SPI1 GPIO BOOT eQEP1 strobe 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A Analog signal Note The pin type shown refers to the input output or high impedance state of the pin function when configured as the the signal name highlighted in bold All multiplexed signals may enter a high impedance...

Page 36: ...P0B GP5 4 BOOT 4 N4 I IPU eQEP0 GPIO SPI0 UART0 SPI0_ENA UART0_CTS EQEP0A GP5 3 BOOT 3 R5 I IPU eQEP0 GPIO SPI0_CLK EQEP1I GP5 2 BOOT 2 T5 I IPD SPI0 eQEP1 GPIO SPI0_SIMO 0 EQEP0S GP5 1 BOOT 1 P6 I IPD SPI0 eQEP0 GPIO SPI0_SOMI 0 EQEP0I GP5 0 BOOT 0 R6 I IPD 1 Boot decoding will be defined in the ROM datasheet 2 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A An...

Page 37: ...nput O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A Analog signal Note The pin type shown refers to the input output or high impedance state of the pin function when configured as the the signal name highlighted in bold All multiplexed signals may enter a high impedance state when the configured function is input only or the configured function supports high Z operatio...

Page 38: ...e reflects the pin function direction for that particular peripheral 2 IPD Internal Pulldown resistor IPU Internal Pullup resistor 3 7 13 Timers Table 3 17 Timers Terminal Functions PIN NO SIGNAL NAME TYPE 1 PULL 2 MUXED DESCRIPTION ZKB TIMER0 UART0_RXD I2C0_SDA TM64P0_IN12 GP5 8 BOOT 8 R3 I IPU Timer0 lower input UART0 I2C0 Timer0 lower GPIO BOOT UART0_TXD I2C0_SCL TM64P0_OUT12 GP5 9 BOOT 9 P3 O ...

Page 39: ...TL0 GP1 1 R9 I O IPU GPIO UHPI half word EMA_BA 1 LCD_D 5 UHPI_HHWIL GP1 13 P8 I O IPU EMIFA LCD GPIO identification control EMIFA McASP EMA_WE UHPI_HRW AXR0 12 GP2 3 BOOT 14 M13 I O IPU UHPI read write GPIO BOOT EMIFA GPIO EMA_CS 2 UHPI_HCS GP2 5 BOOT 15 P7 I O IPU UHPI chip select BOOT EMA_WE_DQM 1 UHPI_HDS2 AXR0 14 GP2 8 P12 I O IPU UHPI data strobe EMIFA McASP0 EMA_OE UHPI_HDS1 AXR0 13 GP2 7 R...

Page 40: ...N GP2 11 B5 I O IPD GPIO master clock McASP0 transmit ACLKX0 ECAP0 APWM0 GP2 12 C5 I O IPD eCAP0 GPIO bit clock McASP0 transmit AFSX0 GP2 13 BOOT 10 D5 I O IPD GPIO BOOT frame sync EMAC GPIO McASP0 receive AHCLKR0 RMII_MHZ_50_CLK GP2 14 BOOT 11 A4 I O IPD BOOT master clock McASP0 receive ACLKR0 ECAP1 APWM1 GP2 15 B4 I O IPD eCAP1 GPIO bit clock McASP0 receive AFSR0 GP3 12 C4 I O IPD GPIO frame syn...

Page 41: ...1 I O IPD GPIO master clock McASP1 receive ACLKR1 ECAP2 APWM2 GP4 12 L2 I O IPD eCAP2 GPIO bit clock McASP1 receive AFSR1 GP4 13 L3 I O IPD GPIO frame sync eHRPWM0 eHRPWM1 McASP1 mute AMUTE1 EPWMTZ GP4 14 D4 I O IPD eHRPWM2 output GPIO McASP2 AXR0 0 RMII_TXD 0 AFSR2 GP3 0 B8 I O IPD AXR0 2 RMII_TXEN AXR2 3 GP3 2 D8 I O IPD McASP0 McASP2 serial EMAC GPIO AXR0 3 RMII_CRS_DV AXR2 2 GP3 3 A7 I O IPD d...

Page 42: ...A NA USB1 PHY data minus USB1_DP A3 A NA USB1 PHY data plus USB1_VDDA33 C1 PWR NA USB1 PHY 3 3 V supply USB1_VDDA18 C2 PWR NA USB1 PHY 1 8 V supply AHCLKX0 AHCLKX2 USB_REFCLKIN B5 I IPD NA USB_REFCLKIN Optional clock input GP2 11 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A Analog signal Note The pin type shown refers to the input output or high impedance s...

Page 43: ...TXD 0 AFSR2 GP3 0 B8 O IPD MDIO AXR0 8 MDIO_D GP3 8 B6 I O IPU MDIO serial data McASP0 GPIO AXR0 7 MDIO_CLK GP3 7 A6 O IPD MDIO clock 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A Analog signal Note The pin type shown refers to the input output or high impedance state of the pin function when configured as the the signal name highlighted in bold All multiple...

Page 44: ...MCSD_DAT 1 UHPI_HD 1 GP0 1 R15 I O IPU EMIFA UHPI GPIO EMA_D 0 MMCSD_DAT 0 UHPI_HD 0 GP0 0 BOOT 12 T13 I O IPU BOOT 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND Ground A Analog signal Note The pin type shown refers to the input output or high impedance state of the pin function when configured as the the signal name highlighted in bold All multiplexed signals may en...

Page 45: ...MA_A 7 LCD_D 0 GP1 7 N10 I O IPD EMIFA GPIO EMA_A 8 LCD_PCLK GP1 8 T11 O IPU LCD pixel clock EMA_A 9 LCD_HSYNC GP1 9 R11 O IPU LCD horizontal sync EMA_A 10 LCD_VSYNC GP1 10 N8 O IPU LCD vertical sync LCD AC bias enable EMA_A 11 LCD_AC_ENB_CS GP1 11 P11 O IPU chip select EMA_A 12 LCD_MCLK GP1 12 N11 O IPU LCD memory clock 1 I Input O Output I O Bidirectional Z High impedance PWR Supply voltage GND ...

Page 46: ...1 Supply and Ground Table 3 25 Supply and Ground Terminal Functions PIN NO SIGNAL NAME TYPE 1 DESCRIPTION ZKB F6 G6 G7 G10 G11 H7 H10 H11 J6 CVDD Core supply PWR Core supply voltage pins J7 J10 J11 J12 K6 K7 K10 K11 L6 RVDD Internal RAM supply H6 H12 PWR Internal ram supply voltage pins B16 E5 E8 E9 E12 F5 F11 F12 G5 DVDD I O supply G12 K5 K12 PWR I O supply voltage pins L5 L11 L12 M5 M8 M9 M12 R1...

Page 47: ...sed USB0_DM No connect Use as USB0 function USB0_DP No connect Use as USB0 function USB0_VDDA33 No connect 3 3V USB0_VDDA18 No connect 1 8V USB0_ID No connect Use as USB0 function USB0_VBUS No connect Use as USB0 function USB0_DRVVBUS GP4 15 No connect or use as alternate function Use as USB0 or alternate function USB0_VDDA12 Internal USB0 PHY output connected to an external 0 22μF filter capacito...

Page 48: ...G module when device reset is deasserted Boot mode selection is determined by the values of the BOOT pins The following boot modes are supported NAND Flash boot 8 bit NAND 16 bit NAND NOR Flash boot NOR Direct boot 8 bit or 16 bit NOR Legacy boot 8 bit or 16 bit NOR AIS boot 8 bit or 16 bit HPI Boot I2C0 I2C1 Boot EEPROM Master Mode External Host Slave Mode SPI0 SPI1 Boot Serial Flash Master Mode ...

Page 49: ...EIDR1 Device Identification Register 1 0x01C1 4010 DIEIDR2 Device Identification Register 2 0x01C1 4014 DIEIDR3 Device Identification Register 3 0x01C1 4018 DEVIDR0 JTAG Identification Register 0x01C1 4020 BOOTCFG Boot Configuration Register Privileged mode 0x01C1 4024 CHIPREVID Silicon Revision Identification Register Privileged mode 0x01C1 4038 KICK0R Kick 0 Register Privileged mode 0x01C1 403C ...

Page 50: ...gister Privileged mode 0x01C1 4158 PINMUX14 Pin Multiplexing Control 14 Register Privileged mode 0x01C1 415C PINMUX15 Pin Multiplexing Control 15 Register Privileged mode 0x01C1 4160 PINMUX16 Pin Multiplexing Control 16 Register Privileged mode 0x01C1 4164 PINMUX17 Pin Multiplexing Control 17 Register Privileged mode 0x01C1 4168 PINMUX18 Pin Multiplexing Control 18 Register Privileged mode 0x01C1 ...

Page 51: ...or the net For a pulldown resistor this should be below the lowest VIL level of all inputs connected to the net For a pullup resistor this should be above the highest VIH level of all inputs on the net A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device which by definition have margin to the VIL and VIH levels Select a pullup pulldown resistor w...

Page 52: ...anent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 All voltage values are with respect to VSS PLL0_VSSA OSCVSS RTC_VSS 3 Up to a max of 24 hours 5...

Page 53: ...ix 40 105 C Commercial 0 375 456 MHz DSP and ARM Industrial D suffix 0 456 MHz FSYSCLK1 6 Operating Frequency Extended A suffix 0 375 MHz SYSCLK1 6 Automotive T suffix 0 375 MHz 1 The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered independently If these power supplies are not isolated CTRL SPLITPOWER 0 RTC_CVDD must be equal to or ...

Page 54: ... 0 to 90 C 1 2V 100 000 D 300 MHz 0 to 90 C 1 2V 100 000 D 375 MHz 0 to 90 C 1 2V 100 000 D 375 MHz 40 to 105 C 1 2V 75 000 1 D 375 MHz 40 to 125 C 1 2V 20 000 D 456 MHz 0 to 90 C 1 3V 100 000 D 456 MHz 40 to 90 C 1 3V 100 000 1 100 000 POH can be achieved at this temperature condition if the device operation is limited to 345 MHz Note Logic functions and parameter values are not assured out of th...

Page 55: ...l output current 4 mA IOZ 4 I O Off state output current VO VDD or VSS Internal pull disabled 35 μA LVCMOS signals 3 pF CI Input capacitance OSCIN and RTC_XI 2 pF CO Output capacitance LVCMOS signals 3 pF 1 These I O specifications apply to regular 3 3V IOs and do not apply to USB0 or USB1 unless specifically indicated USB0 I Os adhere to the USB 2 0 specification USB1 I Os adhere to the USB 1 1 s...

Page 56: ...are tested with an input slew rate of 4 Volts per nanosecond 4 V ns at the device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal Figure 6 1 Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals This load capacitance value does not indicate the maximum load t...

Page 57: ... 2b may be powered up together or 2a first followed by 2b 3 All 1 8V IO supplies USB0_VDDA18 USB1_VDDA18 4 All digital IO and analog 3 3V PHY supplies DVDD USB0_VDDA33 USB1_VDDA33 If both USB0 and USB1 are not used USB0_VDDA33 and USB1_VDDA33 are not required and may be left unconnected Group 3 and group 4 may be powered on in either order 3 then 4 or 4 then 3 but group 4 must be powered on after ...

Page 58: ...ive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST When using this type of JTAG controller assert TRST to intialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations RTCK GP7 14 is maintained active through a POR A summary of the effects of Power On Reset i...

Page 59: ... low 100 ns 2 tsu BPV RSTH Setup time boot pins valid before RESET TRST high 20 ns 3 th RSTH BPV Hold time boot pins valid after RESET TRST high 20 ns 4 td RSTH RESET high to RESETOUT high Warm reset 4096 cycles 3 RESETOUTH RESET high to RESETOUT high Power on Reset 6192 1 RESETOUT is multiplexed with other pin functions See the Terminal Functions table Table 3 5 for details 2 For power on reset P...

Page 60: ...i Z OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 5 Warm Reset RESET active TRST high Timing 60 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 61: ...ommended Typical load capacitance values are 10 20 pF where the load capacitance is the series combination of C1 and C2 The CLKMODE bit in the PLLCTL register must be 0 to use the on chip oscillator If CLKMODE is set to 1 the internal oscillator is disabled Figure 6 6 illustrates the option that uses on chip 1 2V oscillator with external crystal circuit Figure 6 7 illustrates the option that uses ...

Page 62: ...igh external clock on OSCIN 0 4 tc OSCIN ns tw OSCINL Pulse width low external clock on OSCIN 0 4 tc OSCIN ns tt OSCIN Transition time OSCIN 0 25P or 10 1 ns tj OSCIN Period jitter OSCIN 0 02P ns 1 Whichever is smaller P the period of the applied signal Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals 62 Peripheral Information and Electrica...

Page 63: ...ed are as follows PLL Multiplier Control PLLM Software programmable PLL Bypass PLLEN 6 6 1 PLL Device Specific Information The OMAP L137 DSP generates the high frequency internal clocks it requires through an on chip PLL The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6 8 Figure 6 8 PLL External Filtering Components The input to the PLL is either...

Page 64: ...Div PLLM PLLEN AUXCLK 0 1 PLL Post Div CLKMODE 1 0 Square Wave Crystal OSCIN OBSCLK Pin 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 OCSEL OCSRC OSCDIV OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 9 PLL Topology 64 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Docu...

Page 65: ...be chosen such that the PLL output frequency at PLLOUT is between 300 and 600 MHz but the frequency going into the SYSCLK dividers after the post divider cannot exceed the maximum clock frequency defined for the device at a given voltage operating point 6 6 2 Device Clock Generation PLL0 is controlled by PLL Controller 0 The PLLC0 manages the clock ratios alignment and gating for the system clocks...

Page 66: ...SCDIV Oscillator Divider 1 Register OBSCLK 0x01C1 1128 POSTDIV PLL Post Divider Control Register 0x01C1 1138 PLLCMD PLL Controller Command Register 0x01C1 113C PLLSTAT PLL Controller Status Register 0x01C1 1140 ALNCTL PLL Controller Clock Align Control Register 0x01C1 1144 DCHANGE PLLDIV Ratio Change Status Register 0x01C1 1148 CKEN Clock Enable Control Register 0x01C1 114C CKSTAT Clock Status Reg...

Page 67: ... an interrupt vector based unique to each System Interrupt 32 Interrupt Channels Each System Interrupt is mapped to one of the 32 Interrupt Channels Channel Number determines the first level of prioritization Channel 0 is highest priority and 31 lowest If more than one system interrupt is mapped to a channel priority within the channel is determined by system interrupt number 0 highest priority Ho...

Page 68: ... SYSTEM INTERRUPT INTERRUPT NAME SOURCE 0 COMMTX ARM 1 COMMRX ARM 2 NINT ARM 3 PRU_EVTOUT0 PRUSS Interrupt 4 PRU_EVTOUT1 PRUSS Interrupt 5 PRU_EVTOUT2 PRUSS Interrupt 6 PRU_EVTOUT3 PRUSS Interrupt 7 PRU_EVTOUT4 PRUSS Interrupt 8 PRU_EVTOUT5 PRUSS Interrupt 9 PRU_EVTOUT6 PRUSS Interrupt 10 PRU_EVTOUT7 PRUSS Interrupt 11 EDMA3_CC0_CCINT EDMA Channel Controller Region 0 12 EDMA3_CC0_CCERRINT EDMA Cha...

Page 69: ...ler 53 UART_INT1 UART1 54 MCASP_INT McASP0 1 2 Combined RX TX Interrupts 55 PSC1_ALLINT PSC1 56 SPI1_INT SPI1 57 UHPI_ARMINT HPI ARM Interrupt 58 USB0_INT USB0 Interrupt 59 USB1_HCINT USB1 OHCI Host Controller Interrupt 60 USB1_RWAKEUP USB1 Remote Wakeup Interrupt 61 UART2_INT UART2 62 Reserved 63 EHRPWM0 HiResTimer PWM0 Interrupt 64 EHRPWM0TZ HiResTimer PWM0 Trip Zone Interrupt 65 EHRPWM1 HiResTi...

Page 70: ... Timer64P1 Compare 1 84 T64P1_CMPINT2 Timer64P1 Compare 2 85 T64P1_CMPINT3 Timer64P1 Compare 3 86 T64P1_CMPINT4 Timer64P1 Compare 4 87 T64P1_CMPINT5 Timer64P1 Compare 5 88 T64P1_CMPINT6 Timer64P1 Compare 6 89 T64P1_CMPINT7 Timer64P1 Compare 7 90 ARMCLKSTOPREQ PSC0 91 100 Reserved 70 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Docum...

Page 71: ...eserved 0xFFFE E200 0xFFFE E20B SRSR 1 SRSR 3 System Interrupt Status Raw Set Registers 0xFFFE E20C 0xFFFE E27F Reserved 0xFFFE E280 0xFFFE E28B SECR 1 SECR 3 System Interrupt Status Enabled Clear Registers 0xFFFE E28C 0xFFFE E2FF Reserved 0xFFFE E300 0xFFFE E30C ESR 1 ESR 3 System Interrupt Enable Set Registers 0xFFFE E30C 0xFFFE E37F Reserved 0xFFFE E380 0xFFFE E38B ECR 1 ECR 3 System Interrupt ...

Page 72: ...MC 15 MMCSD_INT0 MMCSD MMC SD Interrupt 16 MMCSD_INT1 MMCSD SDIO Interrupt 17 PRU_EVTOUT1 PRU Interrupt 18 EHRPWM1 HiResTimer PWM1 Interrupt 19 USB0_INT USB0 Interrupt 20 USB1_HCINT USB1 OHCI Host Controller Interrupt 21 USB1_RWAKEUP USB1 Remote Wakeup Interrupt 22 PRU_EVTOUT2 PRU Interrupt 23 EHRPWM1TZ HiResTimer PWM1 Trip Zone Interrupt 24 EHRPWM2 HiResTimer PWM2 Interrupt 25 EHRPWM2TZ HiResTime...

Page 73: ...t 63 RTC_IRQS RTC Combined 64 T64P0_TINT34 Timer64P0 Interrupt 34 65 GPIO_B0INT GPIO Bank 0 Interrupt 66 PRU_EVTOUT4 PRU Interrupt 67 SYSCFG_CHIPINT3 SYSCFG_CHIPSIG Register 68 EQEP0 EQEP0 69 UART2_INT UART2 70 PSC0_ALLINT PSC0 71 PSC1_ALLINT PSC1 72 GPIO_B7INT GPIO Bank 7 Interrupt 73 LCDC_INT LCD Controller 74 MPU_BOOTCFG_ERR Shared MPU and SYSCFG Address Protection Error Interrupt 75 77 Reserve...

Page 74: ... 97 EMC_IDMAERR C674x EMC 98 112 Reserved 113 PMC_ED C674x PMC 114 115 Reserved 116 UMC_ED1 C674x UMC 117 UMC_ED2 C674x UMC 118 PDC_INT C674x PDC 119 SYS_CMPA C674x SYS 120 PMC_CMPA C674x PMC 121 PMC_CMPA C674x PMC 122 DMC_CMPA C674x DMC 123 DMC_CMPA C674x DMC 124 UMC_CMPA C674x UMC 125 UMC_CMPA C674x UMC 126 EMC_CMPA C674x EMC 127 EMC_BUSERR C674x EMC 74 Peripheral Information and Electrical Spec...

Page 75: ...ked event flag register 2 0x0180 00AC MEVTFLAG3 Masked event flag register 3 0x0180 00C0 EXPMASK0 Exception mask register 0 0x0180 00C4 EXPMASK1 Exception mask register 1 0x0180 00C8 EXPMASK2 Exception mask register 2 0x0180 00CC EXPMASK3 Exception mask register 3 0x0180 00E0 MEXPFLAG0 Masked exception flag register 0 0x0180 00E4 MEXPFLAG1 Masked exception flag register 1 0x0180 00E8 MEXPFLAG2 Mas...

Page 76: ...pectively Set clear functionality Firmware writes 1 to corresponding bit position s to set or to clear GPIO signal s This allows multiple firmware processes to toggle GPIO output signals without critical section protection disable interrupts program GPIO re enable interrupts to prevent context switching to anther process during GPIO programming Separate Input Output registers Output register in ad...

Page 77: ...ATA45 GPIO Banks 4 and 5 Set Data Register 0x01E2 606C CLR_DATA45 GPIO Banks 4 and 5 Clear Data Register 0x01E2 6070 IN_DATA45 GPIO Banks 4 and 5 Input Data Register 0x01E2 6074 SET_RIS_TRIG45 GPIO Banks 4 and 5 Set Rising Edge Interrupt Register 0x01E2 6078 CLR_RIS_TRIG45 GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register 0x01E2 607C SET_FAL_TRIG45 GPIO Banks 4 and 5 Set Falling Edge Interru...

Page 78: ...GPOL Pulse duration GPn m as output low 2C 1 2 ns 1 This parameter value should not be used as a maximum performance specification Actual performance of back to back accesses of the GPIO is dependent upon internal bus activity 2 C SYSCLK4 period in ns Figure 6 10 GPIO Port Timing 6 8 3 GPIO Peripheral External Interrupts Electrical Data Timing Table 6 13 Timing Requirements for External Interrupts...

Page 79: ...r 0x01C0 031C CCERRCLR EDMA3CC Error Clear Register 0x01C0 0320 EEVAL Error Evaluate Register 0x01C0 0340 DRAE0 DMA Region Access Enable Register for Region 0 0x01C0 0348 DRAE1 DMA Region Access Enable Register for Region 1 0x01C0 0350 DRAE2 DMA Region Access Enable Register for Region 2 0x01C0 0358 DRAE3 DMA Region Access Enable Register for Region 3 0x01C0 0380 QRAE0 QDMA Region Access Enable Re...

Page 80: ...Register 0x01C0 2008 ECR Event Clear Register 0x01C0 2010 ESR Event Set Register 0x01C0 2018 CER Chained Event Register 0x01C0 2020 EER Event Enable Register 0x01C0 2028 EECR Event Enable Clear Register 0x01C0 2030 EESR Event Enable Set Register 0x01C0 2038 SER Secondary Event Register 0x01C0 2040 SECR Secondary Event Clear Register 0x01C0 2050 IER Interrupt Enable Register 0x01C0 2058 IECR Interr...

Page 81: ...or Clear Register 0x01C0 812C 0x01C0 852C ERRDET Error Details Register 0x01C0 8130 0x01C0 8530 ERRCMD Error Interrupt Command Register 0x01C0 8140 0x01C0 8540 RDRATE Read Command Rate Register 0x01C0 8240 0x01C0 8640 SAOPT Source Active Options Register 0x01C0 8244 0x01C0 8644 SASRC Source Active Source Address Register 0x01C0 8248 0x01C0 8648 SACNT Source Active Count Register 0x01C0 824C 0x01C0...

Page 82: ...3CC 0x01C0 87CC DFDST3 Destination FIFO Destination Address Register 3 0x01C0 83D0 0x01C0 87D0 DFBIDX3 Destination FIFO B Index Register 3 0x01C0 83D4 0x01C0 87D4 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3 Table 6 16 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA events Each of the parameter register sets consist of 8 32 bit wo...

Page 83: ... Interrupt 22 GPIO Bank 2 Interrupt 7 GPIO Bank 1 Interrupt 23 GPIO Bank 3 Interrupt 8 UART0 Receive 24 I2C0 Receive 9 UART0 Transmit 25 I2C0 Transmit 10 Timer64P0 Event Out 12 26 I2C1 Receive 11 Timer64P0 Event Out 34 27 I2C1 Transmit 12 UART1 Receive 28 GPIO Bank 4 Interrupt 13 UART1 Transmit 29 GPIO Bank 5 Interrupt 14 SPI0 Receive 30 UART2 Receive 15 SPI0 Transmit 31 UART2 Transmit Copyright 2...

Page 84: ... supports 1 bit and 4 bit ECC calculation on blocks of 512 bytes 6 10 2 EMIFA Synchronous DRAM Memory Support The OMAP L137 ZKB package supports 16 bit SDRAM in addition to the asynchronous memories listed in Section 6 10 1 It has a single SDRAM chip select EMA_CS 0 SDRAM configurations that are supported are One Two and Four Bank SDRAM devices Devices with Eight Nine Ten and Eleven Column Address...

Page 85: ...ports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by board simulation using IBIS models 6 10 4 EMIFA Connection Examples Figure 6 12 illustrates an example of how SDRAM NOR and NAND flash devices might be connected to EMIFA of a OMAP L137 device simultaneously The SDR...

Page 86: ...e EMIFA chip select used for NAND flash is illustrated in Figure 6 13 This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the EMIFA In this case if NAND is the boot memory then the boot image needs to be stored in the NAND area selected by EMA_CS 3 Part of the application image could spill over into the NAND regions selected by other EMIFA chip selec...

Page 87: ...R 2 B NAND FLASH x8 MultiPlane DVDD EMA_WAIT EMA_CS 4 EMA_CS 5 OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 13 OMAP L137 EMIFA Connection Diagram Multiple NAND Flash Planes Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 87 Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 88: ...ister 0x6800 0048 INTMSKSET EMIFA Interrupt Mask Set Register 0x6800 004C INTMSKCLR EMIFA Interrupt Mask Clear Register 0x6800 0060 NANDFCR NAND Flash Control Register 0x6800 0064 NANDFSR NAND Flash Status Register 0x6800 0070 NANDF1ECC NAND Flash 1 ECC Register CS2 Space 0x6800 0074 NANDF2ECC NAND Flash 2 ECC Register CS3 Space 0x6800 0078 NANDF3ECC NAND Flash 3 ECC Register CS4 Space 0x6800 007C...

Page 89: ...CLK rising to EMA_WE_DQM 1 0 invalid 1 ns 7 td CLKH AV Delay time EMA_CLK rising to EMA_A 12 0 and EMA_BA 1 0 valid 7 ns Output hold time EMA_CLK rising to EMA_A 12 0 and EMA_BA 1 0 8 toh CLKH AIV 1 ns invalid 9 td CLKH DV Delay time EMA_CLK rising to EMA_D 15 0 valid 7 ns 10 toh CLKH DIV Output hold time EMA_CLK rising to EMA_D 15 0 invalid 1 ns 11 td CLKH RASV Delay time EMA_CLK rising to EMA_RA...

Page 90: ...8 8 12 10 16 3 5 7 7 11 13 15 9 BASIC SDRAM WRITE OPERATION EMA_CS 0 EMA_WE_DQM 1 0 EMA_RAS EMA_CAS EMA_WE OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 14 EMIFA Basic SDRAM Write Operation Figure 6 15 EMIFA Basic SDRAM Read Operation 90 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Pr...

Page 91: ... E 3 RS E RS E 3 ns EMA_OE low SS 0 4 tsu EMCEL EMOEL Output setup time EMA_CE 5 2 low to 3 0 3 ns EMA_OE low SS 1 Output hold time EMA_OE high to RH E 3 RH E RH E 3 ns EMA_CE 5 2 high SS 0 5 th EMOEH EMCEH Output hold time EMA_OE high to 3 0 3 ns EMA_CE 5 2 high SS 1 Output setup time EMA_BA 1 0 valid to 6 tsu EMBAV EMOEL RS E 3 RS E RS E 3 ns EMA_OE low Output hold time EMA_OE high to 7 th EMOEH...

Page 92: ... 19 WH E 3 WH E WH E 3 ns EMDQMIV EMA_BA 1 0 invalid Output setup time EMA_BA 1 0 valid to 20 tsu EMBAV EMWEL WS E 3 WS E WS E 3 ns EMA_WE low Output hold time EMA_WE high to 21 th EMWEH EMBAIV WH E 3 WH E WH E 3 ns EMA_BA 1 0 invalid Output setup time EMA_A 13 0 valid to 22 tsu EMAV EMWEL WS E 3 WS E WS E 3 ns EMA_WE low Output hold time EMA_WE high to 23 th EMWEH EMAIV WH E 3 WH E WH E 3 ns EMA_...

Page 93: ...E 10 5 9 7 4 8 6 3 1 EMA_ _DQM 1 0 WE OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 16 Asynchronous Memory Read Timing for EMIFA Figure 6 17 Asynchronous Memory Write Timing for EMIFA Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 93 Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 94: ... HOLD 14 OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 18 EMA_WAIT Read Timing Requirements Figure 6 19 EMA_WAIT Write Timing Requirements 94 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 95: ...dicated as crossbar in the figure The EMIFB implements a split transaction internal bus allowing concurrence between reads and writes from the various requesters Figure 6 20 EMIFB Functional Block Diagram EMIFB supports a 3 3V LVCMOS Interface 6 11 1 EMIFB SDRAM Loading Limitations EMIFB supports SDRAM up to 152MHz with up to two SDRAM or asynchronous memory loads Additional loads will limit the S...

Page 96: ...256 32 128 2 32 13 9 1 128 16 64 2 32 13 9 2 256 32 128 2 32 13 9 4 512 64 256 16 2 32 13 10 1 256 32 128 2 32 13 10 2 512 64 256 2 32 13 10 4 1024 128 512 2 32 13 11 1 512 64 256 2 32 13 11 2 1024 128 512 2 32 13 11 4 2048 256 1024 1 The shaded cells indicate configurations that are possible on the EMIFB interface but as of this writing SDRAM memories capable of supporting these densities are not...

Page 97: ...MB_WE_DQM 0 EMB_WE_DQM 1 EMB_D 15 0 EMIFB CE CAS RAS WE CLK CKE BA 1 0 A 11 0 LDQM UDQM DQ 15 0 SDRAM 2M x 16 x 4 Bank OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 21 EMIFB to 2M 16 4 bank SDRAM Interface Figure 6 22 EMIFB to 2M 32 4 bank SDRAM Interface Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 97 Submit Docu...

Page 98: ...M SIZE WIDTH BANKS MEMORY ADDRESS PINS 64M bits 16 4 SDRAM A 11 0 EMIFB EMB_A 11 0 32 4 SDRAM A 10 0 EMIFB EMB_A 10 0 128M bits 16 4 SDRAM A 11 0 EMIFB EMB_A 11 0 32 4 SDRAM A 11 0 EMIFB EMB_A 11 0 256M bits 16 4 SDRAM A 12 0 EMIFB EMB_A 12 0 32 4 SDRAM A 11 0 EMIFB EMB_A 11 0 512M bits 16 4 SDRAM A 12 0 EMIFB EMB_A 12 0 32 4 SDRAM A 12 0 EMIFB EMB_A 12 0 Table 6 27 is a list of the EMIFB register...

Page 99: ...t Priority Register 0xB000 0040 PC1 Performance Counter 1 Register 0xB000 0044 PC2 Performance Counter 2 Register 0xB000 0048 PCC Performance Counter Configuration Register 0xB000 004C PCMRS Performance Counter Master Region Select Register 0xB000 0050 PCT Performance Counter Time Register 0xB000 00C0 IRR Interrupt Raw Register 0xB000 00C4 IMR Interrupt Mask Register 0xB000 00C8 IMSR Interrupt Mas...

Page 100: ...LK rising to 6 toh CLKH DQMIV 1 1 1 1 ns EMB_WE_DQM 3 0 invalid Delay time EMB_CLK rising to EMB_A 12 0 and 7 td CLKH AV 4 25 5 1 ns EMB_BA 1 0 valid Output hold time EMB_CLK rising to EMB_A 12 0 and 8 toh CLKH AIV 1 1 1 1 ns EMB_BA 1 0 invalid 9 td CLKH DV Delay time EMB_CLK rising to EMB_D 31 0 valid 4 25 5 1 ns Output hold time EMB_CLK rising to EMB_D 31 0 10 toh CLKH DIV 1 1 1 1 ns invalid 11 ...

Page 101: ...put hold time EMB_CLK rising to EMB_D 31 0 10 toh CLKH DIV 1 1 0 9 ns invalid 11 td CLKH RASV Delay time EMB_CLK rising to EMB_RAS valid 4 25 5 1 ns 12 toh CLKH RASIV Output hold time EMB_CLK rising to EMB_RAS invalid 1 1 0 9 ns 13 td CLKH CASV Delay time EMB_CLK rising to EMB_CAS valid 4 25 5 1 ns 14 toh CLKH CASIV Output hold time EMB_CLK rising to EMB_CAS invalid 1 1 0 9 ns 15 td CLKH WEV Delay...

Page 102: ...8 8 12 10 16 3 5 7 7 11 13 15 9 BASIC SDRAM WRITE OPERATION EMB_CS 0 EMB_WE_DQM 3 0 EMB_RAS EMB_CAS EMB_WE OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 24 EMIFB Basic SDRAM Write Operation Figure 6 25 EMIFB Basic SDRAM Read Operation 102 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback P...

Page 103: ...NCLR Interrupt enable clear 0x01E1 4020 0x01E1 41FF Reserved 0x01E1 4200 PROG1_MPSAR Programmable range 1 start address 0x01E1 4204 PROG1_MPEAR Programmable range 1 end address 0x01E1 4208 PROG1_MPPA Programmable range 1 memory page protection attributes 0x01E1 420C 0x01E1 420F Reserved 0x01E1 4210 PROG2_MPSAR Programmable range 2 start address 0x01E1 4214 PROG2_MPEAR Programmable range 2 end addr...

Page 104: ... PROG2_MPPA Programmable range 2 memory page protection attributes 0x01E1 521C 0x01E1 521F Reserved 0x01E1 5220 PROG3_MPSAR Programmable range 3 start address 0x01E1 5224 PROG3_MPEAR Programmable range 3 end address 0x01E1 5228 PROG3_MPPA Programmable range 3 memory page protection attributes 0x01E1 522C 0x01E1 522F Reserved 0x01E1 5230 PROG4_MPSAR Programmable range 4 start address 0x01E1 5234 PR...

Page 105: ...mmable range 10 end address 0x01E1 5298 PROG10_MPPA Programmable range 10 memory page protection attributes 0x01E1 529C 0x01E1 529F Reserved 0x01E1 52A0 PROG11_MPSAR Programmable range 11 start address 0x01E1 52A4 PROG11_MPEAR Programmable range 11 end address 0x01E1 52A8 PROG11_MPPA Programmable range 11 memory page protection attributes 0x01E1 52AC 0x01E1 52AF Reserved 0x01E1 52B0 PROG12_MPSAR P...

Page 106: ...Register 1 0x01C4 0010 MMCIM MMC Interrupt Mask Register 0x01C4 0014 MMCTOR MMC Response Time Out Register 0x01C4 0018 MMCTOD MMC Data Read Time Out Register 0x01C4 001C MMCBLEN MMC Block Length Register 0x01C4 0020 MMCNBLK MMC Number of Blocks Register 0x01C4 0024 MMCNBLC MMC Number of Blocks Counter Register 0x01C4 0028 MMCDRR MMC Data Receive Register 0x01C4 002C MMCDXR MMC Data Transmit Regist...

Page 107: ...racteristics Over Recommended Operating Conditions for MMC SD Module see Figure 6 26 through Figure 6 29 No PARAMETER MIN MAX UNIT 7 f CLK Operating frequency MMCSD_CLK 0 52 MHz 8 f CLK_ID Identification mode frequency MMCSD_CLK 0 400 KHz 9 tW CLKL Pulse width MMCSD_CLK low 6 5 ns 10 tW CLKH Pulse width MMCSD_CLK high 6 5 ns 11 tr CLK Rise time MMCSD_CLK 3 ns 12 tf CLK Fall time MMCSD_CLK 3 ns 13 ...

Page 108: ..._CMD 13 7 10 9 13 13 13 OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 26 MMC SD Host Command Timing Figure 6 27 MMC SD Card Response Timing Figure 6 28 MMC SD Host Write Timing Figure 6 29 MMC SD Host Read and Card CRC Status Timing 108 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Pro...

Page 109: ...VECTOR MAC Input Vector Register 0x01E2 3094 MACEOIVECTOR MAC End Of Interrupt Vector Register 0x01E2 30A0 RXINTSTATRAW Receive Interrupt Status Unmasked Register 0x01E2 30A4 RXINTSTATMASKED Receive Interrupt Status Masked Register 0x01E2 30A8 RXINTMASKSET Receive Interrupt Mask Set Register 0x01E2 30AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register 0x01E2 30B0 MACINTSTATRAW MAC Interrupt St...

Page 110: ...504 MACADDRHI MAC Address High Bytes Register Used in Receive Address Matching 0x01E2 3508 MACINDEX MAC Index Register 0x01E2 3600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register 0x01E2 3604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register 0x01E2 3608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register 0x01E2 360C TX3HDP Transmit Channel 3 DMA Head Descripto...

Page 111: ...NCODEERRORS Total number of frames received with alignment code errors Receive Oversized Frames Register 0x01E2 3218 RXOVERSIZED Total number of oversized frames received Receive Jabber Frames Register 0x01E2 321C RXJABBER Total number of jabber frames received Receive Undersized Frames Register 0x01E2 3220 RXUNDERSIZED Total number of undersized frames received 0x01E2 3224 RXFRAGMENTS Receive Fra...

Page 112: ...ble Register 0x01E2 2034 C2RXEN EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register 0x01E2 2038 C2TXEN EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register 0x01E2 203C C2MISCEN EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register 0x01E2 2040 C0RXTHRESHSTAT EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register ...

Page 113: ...CRSDV REFCLK Input Setup Time CRSDV Valid before RMII_MHZ_50_CLK High 4 ns 9 th REFCLK CRSDV Input Hold Time CRSDV Valid after RMII_MHZ_50_CLK High 2 ns 10 tsu RXER REFCLK Input Setup Time RXER Valid before RMII_MHZ_50_CLK High 4 ns 11 th REFCLKR RXER Input Hold Time RXER Valid after RMII_MHZ_50_CLK High 2 ns Note Per the RMII industry specification the RMII reference clock RMII_MHZ_50_CLK must ha...

Page 114: ... MDIO Registers Table 6 42 MDIO Register Memory Map BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 4000 REV Revision Identification Register 0x01E2 4004 CONTROL MDIO Control Register 0x01E2 4008 ALIVE MDIO PHY Alive Status Register 0x01E2 400C LINK MDIO PHY Link Status Register 0x01E2 4010 LINKINTRAW MDIO Link Status Change Interrupt Unmasked Register 0x01E2 4014 LINKINTMASKED MDIO Link Status C...

Page 115: ...DIO_CLK 5 ns 4 tsu MDIO MDIO_CLKH Setup time MDIO_D data input valid before MDIO_CLK high 10 ns 5 th MDIO_CLKH MDIO Hold time MDIO_D data input valid after MDIO_CLK high 0 ns Figure 6 31 MDIO Input Timing Table 6 44 Switching Characteristics Over Recommended Operating Conditions for MDIO Output see Figure 6 32 No PARAMETER MIN MAX UNIT 7 td MDIO_CLKL MDIO Delay time MDIO_CLK low to MDIO_D data out...

Page 116: ...ts First bit delay 0 1 or 2 clocks MSB or LSB first bit order Left or right aligned data words within time slots DIT Mode optional with 384 bit Channel Status and 384 bit User Data registers Extensive error checking and mute generation logic All unused pins GPIO capable Additionally while the OMAP L13x McASP modules are backward compatible with the McASP on previous devices the OMAP L13x McASP inc...

Page 117: ...0x01D0 4064 0x01D0 8064 RMASK Receive format unit bit mask register 0x01D0 0068 0x01D0 4068 0x01D0 8068 RFMT Receive bit stream format register 0x01D0 006C 0x01D0 406C 0x01D0 806C AFSRCTL Receive frame sync control register 0x01D0 0070 0x01D0 4070 0x01D0 8070 ACLKRCTL Receive clock control register 0x01D0 0074 0x01D0 4074 0x01D0 8074 AHCLKRCTL Receive high frequency clock control register 0x01D0 0...

Page 118: ...0148 0x01D0 4148 0x01D0 8148 DITUDRB0 Right odd TDM time slot channel user data register DIT mode 0 0x01D0 014C 0x01D0 414C 0x01D0 814C DITUDRB1 Right odd TDM time slot channel user data register DIT mode 1 0x01D0 0150 0x01D0 4150 0x01D0 8150 DITUDRB2 Right odd TDM time slot channel user data register DIT mode 2 0x01D0 0154 0x01D0 4154 0x01D0 8154 DITUDRB3 Right odd TDM time slot channel user data...

Page 119: ...84 RBUF1 2 Receive buffer register for serializer 1 0x01D0 0288 0x01D0 4288 0x01D0 8288 RBUF2 3 Receive buffer register for serializer 2 0x01D0 028C 0x01D0 428C 0x01D0 828C RBUF3 3 Receive buffer register for serializer 3 0x01D0 0290 0x01D0 4290 0x01D0 8290 RBUF4 3 Receive buffer register for serializer 4 0x01D0 0294 0x01D0 4294 0x01D0 8294 RBUF5 3 Receive buffer register for serializer 5 0x01D0 0...

Page 120: ...ive and inactive serializers Starts at the lowest serializer at the beginning of each time slot Writes to DMA port only if XBUSEL 0 in XFMT Table 6 48 McASP AFIFO Registers Accessed Through Peripheral Configuration Port McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01D0 1000 0x01D0 5000 0x01D0 9000 AFIFOREV AFIFO revision identification register 0x01D0 ...

Page 121: ...ime AFSX0 input after ACLKX0 external input 0 9 Hold time AFSR0 input after ACLKR0 external output 3 0 9 Hold time AFSX0 input after ACLKX0 external output 0 9 Setup time AXR0 n input to ACLKR0 internal 3 9 4 Setup time AXR0 n input to ACLKX0 internal 4 9 4 Setup time AXR0 n input to ACLKR0 external input 3 2 9 7 tsu AXR ACLKRX ns Setup time AXR0 n input to ACLKX0 external input 4 2 9 Setup time A...

Page 122: ... 8 Delay time ACLKX0 internal AFSX output 0 5 8 Delay time ACLKR0 external input AFSR output 7 2 5 11 6 13 td ACLKRX AFSRX ns Delay time ACLKX0 external input AFSX output 2 5 11 6 Delay time ACLKR0 external output AFSR output 7 2 5 11 6 Delay time ACLKX0 external output AFSX output 2 5 11 6 Delay time ACLKX0 internal AXR0 n output 0 5 8 14 td ACLKX AXRV Delay time ACLKX0 external input AXR0 n outp...

Page 123: ...ter ACLKX1 external input 0 7 Hold time AFSR1 input after ACLKR1 external output 3 0 7 Hold time AFSX1 input after ACLKX1 external output 0 7 Setup time AXR1 n input to ACLKR1 internal 3 10 4 Setup time AXR1 n input to ACLKX1 internal 4 10 4 Setup time AXR1 n input to ACLKR1 external input 3 2 6 7 tsu AXR ACLKRX ns Setup time AXR1 n input to ACLKX1 external input 4 2 6 Setup time AXR1 n input to A...

Page 124: ...lay time ACLKX1 internal AFSX output 0 5 6 7 Delay time ACLKR1 external input AFSR output 7 3 4 13 8 13 td ACLKRX AFSRX ns Delay time ACLKX1 external input AFSX output 3 4 13 8 Delay time ACLKR1 external output AFSR output 7 3 4 13 8 Delay time ACLKX1 external output AFSX output 3 4 13 8 Delay time ACLKX1 internal AXR1 n output 0 5 6 7 14 td ACLKX AXRV Delay time ACLKX1 external input AXR1 n outpu...

Page 125: ...KX2 external input 1 3 Hold time AFSR2 input after ACLKR2 external output 3 1 3 Hold time AFSX2 input after ACLKX2 external output 1 3 Setup time AXR2 n input to ACLKR2 internal 3 10 Setup time AXR2 n input to ACLKX2 internal 4 10 Setup time AXR2 n input to ACLKR2 external input 3 1 6 7 tsu AXR ACLKRX ns Setup time AXR2 n input to ACLKX2 external input 4 1 6 Setup time AXR2 n input to ACLKR2 exter...

Page 126: ...4 2 8 Delay time ACLKX2 internal AFSX output 1 4 2 8 Delay time ACLKR2 external input AFSR output 7 2 1 10 13 td ACLKRX AFSRX ns Delay time ACLKX2 external input AFSX output 2 1 10 Delay time ACLKR2 external output AFSR output 7 2 1 10 Delay time ACLKX2 external output AFSX output 2 1 10 Delay time ACLKX2 internal AXR2 n output 1 4 2 8 14 td ACLKX AXRV Delay time ACLKX2 external input AXR2 n outpu...

Page 127: ...137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 A For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver is configured for falling edge to shift data in B For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configured for rising edge to shift data in Figure 6 34 McASP Inp...

Page 128: ...XP 1 A OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com A For CLKRP CLKXP 1 the McASP transmitter is configured for falling edge to shift data out and the McASP receiver is configured for rising edge to shift data in B For CLKRP CLKXP 0 the McASP transmitter is configured for rising edge to shift data out and the McASP receiver is configured for falling edge to shift data in Figure 6...

Page 129: ... the SPIx_SOMI pin when SPIx_SCS is held low In slave mode SPIx_ENA is an optional output The SPIx_ENA output provides the status of the internal transmit buffer SPIDAT0 1 registers In four pin mode with the enable option SPIx_ENA is asserted only when the transmit buffer is full indicating that the slave is ready to begin another transfer In five pin mode the SPIx_ENA is additionally qualified by...

Page 130: ...SPIx_ENA SPIx_ENA SPIx_SCS SPIx_SCS OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 37 Illustration of SPI Master to SPI Slave Connection 130 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 131: ...Control Register 5 Pin Data Clear 0x01C4 102C 0x01E1 202C Reserved Reserved Do not write to this register 0x01C4 1030 0x01E1 2030 Reserved Reserved Do not write to this register 0x01C4 1034 0x01E1 2034 Reserved Reserved Do not write to this register 0x01C4 1038 0x01E1 2038 SPIDAT0 Shift Register 0 without format select 0x01C4 103C 0x01E1 203C SPIDAT1 Shift Register 1 with format select 0x01C4 1040...

Page 132: ...K falling Polarity 1 Phase 1 5 from SPI0_CLK rising Polarity 0 Phase 0 0 5tc SPC M 3 from SPI0_CLK falling Polarity 0 Phase 1 0 5tc SPC M 3 Output hold time SPI0_SIMO from SPI0_CLK rising 6 toh SPC_SIMO M valid after ns Polarity 1 Phase 0 receive edge of SPI0_CLK 0 5tc SPC M 3 from SPI0_CLK rising Polarity 1 Phase 1 0 5tc SPC M 3 from SPI0_CLK falling Polarity 0 Phase 0 0 to SPI0_CLK falling Polar...

Page 133: ...y 1 Phase 0 receive edge of SPI0_CLK 0 5tc SPC S 3 from SPI0_CLK rising Polarity 1 Phase 1 0 5tc SPC S 3 from SPI0_CLK falling Polarity 0 Phase 0 0 to SPI0_CLK falling Polarity 0 Phase 1 0 Input Setup Time SPI0_SIMO valid to SPI0_CLK rising 15 tsu SIMO_SPC S before ns Polarity 1 Phase 0 receive edge of SPI0_CLK 0 to SPI0_CLK rising Polarity 1 Phase 1 0 to SPI0_CLK falling Polarity 0 Phase 0 5 from...

Page 134: ...r Timings 4 Pin Chip Select Option 2 3 No PARAMATER MIN MAX UNIT Polarity 0 Phase 0 2P 5 to SPI0_CLK rising Polarity 0 Phase 1 0 5tc SPC M 2P 5 to SPI0_CLK rising Delay from SPI0_SCS active to first 19 td SCS_SPC M ns SPI0_CLK 4 5 Polarity 1 Phase 0 2P 5 to SPI0_CLK falling Polarity 1 Phase 1 0 5tc SPC M 2P 5 to SPI0_CLK falling Polarity 0 Phase 0 0 5tc SPC M P 3 from SPI0_CLK falling Polarity 0 P...

Page 135: ...c SPC M 2P 5 to SPI0_CLK falling Polarity 0 Phase 0 3P 3 6 to SPI0_CLK rising Polarity 0 Phase 1 0 5tc SPC M 3P 3 6 Delay from assertion of to SPI0_CLK rising 23 td ENA_SPC M SPI0_ENA low to first ns Polarity 1 Phase 0 SPI0_CLK edge 10 3P 3 6 to SPI0_CLK falling Polarity 1 Phase 1 0 5tc SPC M 3P 3 6 to SPI0_CLK falling 1 These parameters are in addition to the general timings for SPI master modes ...

Page 136: ... 2 3 No PARAMATER MIN MAX UNIT Required delay from SPI0_SCS asserted at slave to first 25 td SCSL_SPC S 2P ns SPI0_CLK edge at slave Polarity 0 Phase 0 0 5tc SPC M P 5 from SPI0_CLK falling Polarity 0 Phase 1 P 5 Required delay from final from SPI0_CLK falling 26 td SPC_SCSH S SPI0_CLK edge before ns Polarity 1 Phase 0 SPI0_SCS is deasserted 0 5tc SPC M P 5 from SPI0_CLK rising Polarity 1 Phase 1 ...

Page 137: ...ble 6 57 2 P SYSCLK2 period 3 Figure shows only Polarity 0 Phase 0 as an example Table gives parameters for all four slave clocking modes 4 SPI0_ENA is driven low after the transmission completes if the SPIINT0 ENABLE_HIGHZ bit is programmed to 0 Otherwise it is 3 stated If 3 stated an external pullup resistor should be used to provide a valid level to the master This option is useful when tying s...

Page 138: ...to SPI1_CLK falling Polarity 0 Phase 1 0 Input Setup Time SPI1_SOMI valid to SPI1_CLK rising 7 tsu SOMI_SPC M before ns Polarity 1 Phase receive edge of SPI1_CLK 0 0 to SPI1_CLK rising Polarity 1 Phase 1 0 to SPI1_CLK falling Polarity 0 Phase 0 5 from SPI1_CLK falling Polarity 0 Phase 1 5 Input Hold Time SPI1_SOMI valid from SPI1_CLK rising 8 tih SPC_SOMI M after ns Polarity 1 Phase receive edge o...

Page 139: ...ase 1 0 5tc SPC S 3 from SPI1_CLK falling Polarity 0 Phase 0 0 to SPI1_CLK falling Polarity 0 Phase 1 0 Input Setup Time SPI1_SIMO valid to SPI1_CLK rising 15 tsu SIMO_SPC S before ns Polarity 1 Phase 0 receive edge of SPI1_CLK 0 to SPI1_CLK rising Polarity 1 Phase 1 0 to SPI1_CLK falling Polarity 0 Phase 0 5 from SPI1_CLK falling Polarity 0 Phase 1 5 Input Hold Time SPI1_SIMO valid from SPI1_CLK ...

Page 140: ...mings 4 Pin Chip Select Option 2 3 No PARAMATER MIN MAX UNIT Polarity 0 Phase 0 2P 5 to SPI1_CLK rising Polarity 0 Phase 1 0 5tc SPC M 2P 5 to SPI1_CLK rising Delay from SPI1_SCS active to first 19 td SCS_SPC M ns SPI1_CLK 4 5 Polarity 1 Phase 0 2P 5 to SPI1_CLK falling Polarity 1 Phase 1 0 5tc SPC M 2P 5 to SPI1_CLK falling Polarity 0 Phase 0 0 5tc SPC M P 3 from SPI1_CLK falling Polarity 0 Phase...

Page 141: ...0 5tc SPC M 2P 5 to SPI1_CLK falling Polarity 0 Phase 0 3P 3 to SPI1_CLK rising Polarity 0 Phase 1 0 5tc SPC M 3P 3 Delay from assertion of to SPI1_CLK rising 23 td ENA_SPC M SPI1_ENA low to first ns Polarity 1 Phase 0 SPI1_CLK edge 10 3P 3 to SPI1_CLK falling Polarity 1 Phase 1 0 5tc SPC M 3P 3 to SPI1_CLK falling 1 These parameters are in addition to the general timings for SPI master modes Tabl...

Page 142: ... S P 19 ns SPI1_SOMI valid Delay from master deasserting SPI1_SCS to slave 3 stating 28 tdis SCSH_SOMI S P 19 ns SPI1_SOMI 1 These parameters are in addition to the general timings for SPI slave modes Table 6 65 2 P SYSCLK2 period 3 Figure shows only Polarity 0 Phase 0 as an example Table gives parameters for all four slave clocking modes Table 6 71 Additional 1 SPI1 Slave Timings 5 Pin Option 2 3...

Page 143: ...ing high SPI1_ENA 4 2 5 P 19 from SPI1_CLK rising Polarity 1 Phase 1 2 5 P 19 from SPI1_CLK falling 4 SPI1_ENA is driven low after the transmission completes if the SPIINT0 ENABLE_HIGHZ bit is programmed to 0 Otherwise it is 3 stated If 3 stated an external pullup resistor should be used to provide a valid level to the master This option is useful when tying several SPI slave devices to a single m...

Page 144: ... MO n MI 0 MI 1 MI n 1 MI n 6 6 7 7 7 7 8 8 8 8 3 2 6 1 4 4 4 4 5 5 5 6 MASTER MODE POLARITY 0 PHASE 0 MASTER MODE POLARITY 0 PHASE 1 MASTER MODE POLARITY 1 PHASE 0 MASTER MODE POLARITY 1 PHASE 1 5 OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 38 SPI Timings Master Mode 144 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorpor...

Page 145: ... 0 SO 1 SO n 1 SO n 14 14 15 15 15 15 16 16 16 16 11 10 14 9 12 12 12 12 13 13 13 13 14 SLAVE MODE POLARITY 0 PHASE 0 SLAVE MODE POLARITY 0 PHASE 1 SLAVE MODE POLARITY 1 PHASE 0 SLAVE MODE POLARITY 1 PHASE 1 OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 39 SPI Timings Slave Mode Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Speci...

Page 146: ... 0 MI 1 MI n 1 MI n 17 19 21 22 23 20 18 20 18 MASTER MODE 4 PIN WITH ENABLE MASTER MODE 5 PIN A DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3 STATE REQUIRES EXTERNAL PULLUP DESEL A DESEL A OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 40 SPI Timings Master Mode 4 Pin and 5 Pin 146 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments In...

Page 147: ...0 28 25 25 27 29 SLAVE MODE 4 PIN WITH ENABLE SLAVE MODE 4 PIN WITH CHIP SELECT SLAVE MODE 5 PIN DESEL A DESEL A A DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3 STATE REQUIRES EXTERNAL PULLUP OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 41 SPI Timings Slave Mode 4 Pin and 5 Pin Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifi...

Page 148: ... or voltage amplitude derived from cuty cycle encoded current voltage sensors The ECAP module described in this specification includes the following features 32 bit time base 4 event time stamp registers each 32 bits Edge polarity selection for up to 4 sequenced time stamp capture events Interrupt on either of the 4 events Single shot capture of up to 4 event time stamps Continuous mode capture of...

Page 149: ...COut SYNCIn Event qualifier Polarity select Polarity select Polarity select Polarity select CTR PRD CTR_OVF 4 PWM compare logic CTR 0 31 PRD 0 31 CMP 0 31 CTR CMP CTR PRD CTR_OVF OVF APWM mode Delta mode SYNC 4 Capture events CEVT 1 4 APRD shadow 32 32 MODE SELECT OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 42 eCAP Functional Block Diagram Copyright 2008 2014 Texas Inst...

Page 150: ...Register 2 0x01F0 602C 0x01F0 702C 0x01F0 802C ECEINT Capture Interrupt Enable Register 0x01F0 602E 0x01F0 702E 0x01F0 802E ECFLG Capture Interrupt Flag Register 0x01F0 6030 0x01F0 7030 0x01F0 8030 ECCLR Capture Interrupt Clear Register 0x01F0 6032 0x01F0 7032 0x01F0 8032 ECFRC Capture Interrupt Force Register 0x01F0 605C 0x01F0 705C 0x01F0 805C REVID Revision ID Table 6 73 shows the eCAP timing r...

Page 151: ...CTMR QCPRD 16 16 QCAPCTL EQEPxENCLK SYSCLK2 Data bus To CPU Interrupt Controller OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 6 19 Enhanced Quadrature Encoder eQEP Peripheral The OMAP L137 device contains up to two enhanced quadrature encoder eQEP modules See the OMAP L137 Applications Processor DSP Peripherals Overview Reference Guide SPRUGA6 for more details Figure 6 43 eQEP Fu...

Page 152: ...upt Flag Register 0x01F0 9034 0x01F0 A034 QCLR eQEP Interrupt Clear Register 0x01F0 9036 0x01F0 A036 QFRC eQEP Interrupt Force Register 0x01F0 9038 0x01F0 A038 QEPSTS eQEP Status Register 0x01F0 903A 0x01F0 A03A QCTMR eQEP Capture Timer 0x01F0 903C 0x01F0 A03C QCPRD eQEP Capture Period Register 0x01F0 903E 0x01F0 A03E QCTMRLAT eQEP Capture Timer Latch 0x01F0 9040 0x01F0 A040 QCPRDLAT eQEP Capture ...

Page 153: ... High Resolution Pulse Width Modulator eHRPWM The OMAP L137 device contains up to three enhanced PWM Modules eHRPWM Figure 6 44 shows a block diagram of multiple eHRPWM modules Figure 4 4 shows the signal interconnections with the eHRPWM See the OMAP L137 Applications Processor DSP Peripherals Overview Reference Guide SPRUGA6 for more details Figure 6 44 Multiple PWM Modules in a OMAP L137 System ...

Page 154: ... CC CMPB active 16 CTR CMPB CMPB shadow 16 CMPAHR 8 EPWMA EPWMB Dead band DB PWM chopper PC Trip zone TZ CTR ZERO EPWMxA EPWMxB EPWMxTZINT TZ HiRes PWM HRPWM CTR PRD CTR ZERO CTR CMPB CTR CMPA CTR_Dir Event trigger and interrupt ET EPWMxINT CTR ZERO OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 45 eHRPWM Sub Modules Showing Critical Internal Signal Interconnections 154 Pe...

Page 155: ...BMODULE REGISTER 0x01F0 001E 0x01F0 201E 0x01F0 401E DBCTL 1 No Dead Band Generator Control Register 0x01F0 0020 0x01F0 2020 0x01F0 4020 DBRED 1 No Dead Band Generator Rising Edge Delay Count Register 0x01F0 0022 0x01F0 2022 0x01F0 4022 DBFED 1 No Dead Band Generator Falling Edge Delay Count Register PWM CHOPPER SUBMODULE REGISTERS 0x01F0 003C 0x01F0 203C 0x01F0 403C PCCTL 1 No PWM Chopper Control...

Page 156: ...able delay td TZ PWM HZ Delay time trip input active to PWM Hi Z no additional 20 ns programmable delay 6 20 2 Trip Zone Input Timing A PWM refers to all the PWM pins in the device The state of the PWM pins after TZ is taken high depends on the PWM recovery software Figure 6 46 PWM Hi Z Characteristics Table 6 81 Trip Zone input Timing Requirements PARAMETER MIN MAX UNIT tw TZ Pulse duration TZx i...

Page 157: ... registers Table 6 83 LCD Controller LCDC Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E1 3000 REVID LCD Revision Identification Register 0x01E1 3004 LCD_CTRL LCD Control Register 0x01E1 3008 LCD_STAT LCD Status Register 0x01E1 300C LIDD_CTRL LCD LIDD Control Register 0x01E1 3010 LIDD_CS0_CONF LCD LIDD CS0 Configuration Register 0x01E1 3014 LIDD_CS0_ADDR LCD LIDD CS0 Address Read Write ...

Page 158: ..._MCLK high to LCD_D 15 0 invalid write 0 5 10 ns 6 td LCD_E_A Delay time LCD_MCLK high to LCD_AC_ENB_CS low 0 5 7 ns 7 td LCD_E_I Delay time LCD_MCLK high to LCD_AC_ENB_CS high 0 5 7 ns 8 td LCD_A_A Delay time LCD_MCLK high to LCD_VSYNC low 0 5 8 ns 9 td LCD_A_I Delay time LCD_MCLK high to LCD_VSYNC high 0 5 8 ns 10 td LCD_W_A Delay time LCD_MCLK high to LCD_HSYNC low 0 5 8 ns 11 td LCD_W_I Delay ...

Page 159: ...2 13 10 11 Not Used LCD_D 7 0 14 17 16 Read Data 15 4 5 E0 E1 12 13 Data 7 0 Write Instruction OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 48 Character Display HD44780 Read Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 159 Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 160: ...63 1 15 CS_DELAY 5 4 5 6 7 6 7 8 9 12 13 Write Address Write Data 12 13 10 11 10 11 Data 15 0 OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 49 Micro Interface Graphic Display 6800 Write 160 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 161: ...63 1 15 CS_DELAY 5 14 15 6 7 6 7 8 9 12 13 17 16 Write Address Read Data 10 11 12 13 Data 15 0 OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 50 Micro Interface Graphic Display 6800 Read Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 161 Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 162: ...1 15 CS_DELAY 14 15 6 7 6 7 8 9 12 13 17 16 14 17 16 15 12 13 Data 15 0 R_SU 0 31 Read Status OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 51 Micro Interface Graphic Display 6800 Status 162 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 163: ...E W_HOLD 0 31 1 63 1 15 CS_DELAY 5 4 5 6 7 6 7 8 9 10 11 Write Address Write Data 10 11 OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 52 Micro Interface Graphic Display 8080 Write Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 163 Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 164: ... 1 63 1 15 CS_DELAY 5 14 15 6 7 6 7 8 9 12 13 17 16 Read Data 10 11 Data 15 0 Write Address OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 53 Micro Interface Graphic Display 8080 Read 164 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 165: ... 15 6 7 6 8 12 13 17 16 Read Status 14 17 16 Read Data 15 12 13 Data 15 0 7 9 R_SU 0 31 OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 54 Micro Interface Graphic Display 8080 Status Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 165 Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 166: ...k through the LCD RASTER_TIMING_2 register In Figure 6 56 through Figure 6 59 all signal polarity and activation edges are based on the default LCD RASTER_TIMING_2 register settings Frame to frame timing is derived through the following parameters in the LCD RASTER_TIMING_1 register Vertical front porch VFP Vertical sync pulse width VSW Vertical back porch VBP Lines per panel LPP Line to line timi...

Page 167: ...Data Pixels From 1 to P Data Lines From 1 to L 1 OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 55 LCD Raster Mode Display Format Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 167 Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 168: ...11 LCD_PCLK LCD_D 15 0 1 1 2 2 P 2 P 1 2 1 1 2 PLL 16 1 to 1024 HBP 1 to 256 Line 1 1 to 256 HFP 1 to 64 HSW PLL 16 1 to 1024 Line 2 Data LCD_AC_ENB_CS Enable OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 56 LCD Raster Mode Active 168 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Produ...

Page 169: ...L 1 P L 1 1 L 3 P L 3 1 to 64 VSW 1 1 to 64 VFP 0 VBP 0 VFP 0 VBP 0 FP Data CP Data Passive STN LCD_AC_ENB_CS M ACB 0 to 255 ACB 0 to 255 1 4 P 4 1 3 P 3 1 2 P 2 1 L P L 1 6 P 6 1 2 P 2 1 1 P 1 1 L P L 1 to 256 OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 57 LCD Raster Mode Passive Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical S...

Page 170: ...e LCD_AC_ENB_CS LCD_D 7 0 passive mode 1 L 2 1 P 1 P L 2 L 1 1 10 11 8 6 4 4 5 5 1 2 3 1 2 3 VSW 1 VFP 0 VBP 0 OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 58 LCD Raster Mode Control Signal Activation 170 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 171: ...CD_D 7 0 passive mode 1 1 2 2 P 2 P 1 2 1 1 2 10 11 9 7 4 5 1 2 3 VSW 1 VFP 0 VBP 0 P 1 1 1 2 1 4 5 1 3 4 Line 2 for passive OMAP L137 www ti com SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 Figure 6 59 LCD Raster Mode Control Signal Deactivation Copyright 2008 2014 Texas Instruments Incorporated Peripheral Information and Electrical Specifications 171 Submit Documentation Feedback Product Folder Lin...

Page 172: ...iod Register 12 0x01C2 001C 0x01C2 101C PRD34 Timer Period Register 34 0x01C2 0020 0x01C2 1020 TCR Timer Control Register 0x01C2 0024 0x01C2 1024 TGCR Timer Global Control Register 0x01C2 0028 0x01C2 1028 WDTCR Watchdog Timer Control Register 0x01C2 0034 0x01C2 1034 REL12 Timer Reload Register 12 0x01C2 0038 0x01C2 1038 REL34 Timer Reload Register 34 0x01C2 003C 0x01C2 103C CAP12 Timer Capture Reg...

Page 173: ...64Px_IN12 frequency is 27 MHz use C 37 037 ns 3 Whichever is smaller P the period of the applied signal Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals Figure 6 60 Timer Timing Table 6 89 Switching Characteristics Over Recommended Operating Conditions for Timer Output 1 No PARAMETER MIN MAX UNIT 5 tw TOUTH Pulse duration TM64P0_OUT12 high ...

Page 174: ... DMA Requests OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com 6 23 Inter Integrated Circuit Serial Ports I2C0 I2C1 6 23 1 I2C Device Specific Information Having two I2C modules on the OMAP L137 simplifies system architecture since one module may be used by the DSP to control local peripherals ICs DACs ADCs etc while the other may be used to communicate with other controllers in a sy...

Page 175: ...ister 0x01C2 2020 0x01E2 8020 ICDXR I2C Data Transmit Register 0x01C2 2024 0x01E2 8024 ICMDR I2C Mode Register 0x01C2 2028 0x01E2 8028 ICIVR I2C Interrupt Vector Register 0x01C2 202C 0x01E2 802C ICEMDR I2C Extended Mode Register 0x01C2 2030 0x01E2 8030 ICPSC I2C Prescaler Register 0x01C2 2034 0x01E2 8034 REVID1 I2C Revision Identification Register 1 0x01C2 2038 0x01E2 8038 REVID2 I2C Revision Iden...

Page 176: ... SCLH Setup time I2Cx_SDA before I2Cx_SCL high ns Fast Mode 100 Standard Mode 0 7 th SDA SCLL Hold time I2Cx_SDA after I2Cx_SCL low μs Fast Mode 0 0 9 Standard Mode 4 7 8 tw SDAH Pulse duration I2Cx_SDA high μs Fast Mode 1 3 Standard Mode 1000 9 tr SDA Rise time I2Cx_SDA ns Fast Mode 20 0 1Cb 300 Standard Mode 1000 10 tr SCL Rise time I2Cx_SCL ns Fast Mode 20 0 1Cb 300 Standard Mode 300 11 tf SDA ...

Page 177: ... μs Fast Mode 1 3 Standard Mode 4 20 tw SCLH Pulse duration I2Cx_SCL high μs Fast Mode 0 6 Standard Mode 250 21 tsu SDAV SCLH Setup time I2Cx_SDA valid before I2Cx_SCL high ns Fast Mode 100 Standard Mode 0 22 th SCLL SDAV Hold time I2Cx_SDA valid after I2Cx_SCL low μs Fast Mode 0 0 9 Standard Mode 4 7 23 tw SDAH Pulse duration I2Cx_SDA high μs Fast Mode 1 3 Standard Mode 4 28 tsu SCLH SDAH Setup t...

Page 178: ..._SCL 16 26 24 OMAP L137 SPRS563G SEPTEMBER 2008 REVISED JUNE 2014 www ti com Figure 6 64 I2C Transmit Timings 178 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links OMAP L137 ...

Page 179: ...3 is the list of UART registers Table 6 93 UART Registers UART0 UART1 UART2 ACRONYM REGISTER DESCRIPTION BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01C4 2000 0x01D0 C000 0x01D0 D000 RBR Receiver Buffer Register read only 0x01C4 2000 0x01D0 C000 0x01D0 D000 THR Transmitter Holding Register write only 0x01C4 2004 0x01D0 C004 0x01D0 D004 IER Interrupt Enable Register 0x01C4 2008 0x01D0 C008 0x01D0 D008...

Page 180: ... UTXDB Pulse duration transmit data bit TXDn U 2 U 2 ns 3 tw UTXSB Pulse duration transmit start bit U 2 U 2 ns 1 U UART baud time 1 programmed baud rate 2 D UART input clock in MHz The UART s input clock source is PLL0_SYSCLK2 3 E UART divisor x UART sampling rate The UART divisor is set through the UART divisor latch registers DLL and DLH The UART sampling rate is set through the over sampling m...

Page 181: ...Start Register 0x01E2 5044 HCLSTHRESHOLD HC Low Speed Threshold Register 0x01E2 5048 HCRHDESCRIPTORA HC Root Hub A Register 0x01E2 504C HCRHDESCRIPTORB HC Root Hub B Register 0x01E2 5050 HCRHSTATUS HC Root Hub Status Register 0x01E2 5054 HCRHPORTSTATUS1 HC Port 1 Status and Control Register 2 0x01E2 5058 HCRHPORTSTATUS2 HC Port 2 Status and Control Register 3 1 Restrictions apply to the physical a...

Page 182: ...z or greater is recommended to avoid data throughput reduction Table 6 98 is the list of USB OTG registers Table 6 98 Universal Serial Bus OTG USB0 Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 0000 REVID Revision Register 0x01E0 0004 CTRLR Control Register 0x01E0 0008 STATR Status Register 0x01E0 000C EMUR Emulation Register 0x01E0 0010 MODE Mode Register 0x01E0 0014 AUTOREQ Autorequ...

Page 183: ...eive Endpoint Index register set to select Endpoints 1 4 0x01E0 0418 COUNT0 Number of Received Bytes in Endpoint 0 FIFO Index register set to select Endpoint 0 RXCOUNT Number of Bytes in Host Receive Endpoint FIFO Index register set to select Endpoints 1 4 0x01E0 041A HOST_TYPE0 Defines the speed of Endpoint 0 HOST_TXTYPE Sets the operating speed transaction protocol and peripheral endpoint number...

Page 184: ...hub TARGET ENDPOINT 1 CONTROL REGISTERS VALID ONLY IN HOST MODE 0x01E0 0488 TXFUNCADDR Address of the target function that has to be accessed through the associated Transmit Endpoint 0x01E0 048A TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 0x01E0 048B TXHU...

Page 185: ...get function that has to be accessed through the associated Transmit Endpoint 0x01E0 04A2 TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 0x01E0 04A3 TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint This is used only ...

Page 186: ...r for the host Transmit endpoint 0x01E0 052B HOST_TXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint 0x01E0 052C HOST_RXTYPE Sets the operating speed transaction protocol and peripheral endpoint number for the host Receive endpoint 0x01E0 052D HOST_RXINTERVAL Sets the polling interval for Interrupt ISOC t...

Page 187: ...ceive Channel 0 Global Configuration Register 0x01E0 180C RXHPCRA 0 Receive Channel 0 Host Packet Configuration Register A 0x01E0 1810 RXHPCRB 0 Receive Channel 0 Host Packet Configuration Register B 0x01E0 1820 TXGCR 1 Transmit Channel 1 Global Configuration Register 0x01E0 1828 RXGCR 1 Receive Channel 1 Global Configuration Register 0x01E0 182C RXHPCRA 1 Receive Channel 1 Host Packet Configurati...

Page 188: ... Base Address Register 0x01E0 50F4 QMEMRCTRL 15 Memory Region 15 Control Register 0x01E0 600C CTRLD 0 Queue Manager Queue 0 Control Register D 0x01E0 601C CTRLD 1 Queue Manager Queue 1 Control Register D 0x01E0 63FC CTRLD 63 Queue Manager Queue 63 Status Register D 0x01E0 6800 QSTATA 0 Queue Manager Queue 0 Status Register A 0x01E0 6804 QSTATB 0 Queue Manager Queue 0 Status Register B 0x01E0 6808 ...

Page 189: ...unction Driver jitter next transition 25 2 3 ns 6 tjr source PT Source Host Driver jitter paired transition 4 1 1 3 ns tjr FUNC PT Function Driver jitter paired transition 10 1 3 ns 7 tw EOPT Pulse duration EOP transmitter 5 1250 1500 160 175 ns 8 tw EOPR Pulse duration EOP receiver 5 670 82 ns 9 t DRATE Data Rate 1 5 12 480 Mb s 10 ZDRV Driver Output Resistance 40 5 49 5 40 5 49 5 Ω 11 ZINP Recei...

Page 190: ...ection Register 2 0x01E1 001C GPIO_DAT2 General Purpose IO Data Register 2 0x01E1 0020 GPIO_DIR3 General Purpose IO Direction Register 3 0x01E1 0024 GPIO_DAT3 General Purpose IO Data Register 3 01E1 0028 Reserved 01E1 002C Reserved The Host and the CPU both 01E1 0030 HPIC HPI control register have read write access to the HPIC register HPIA HPI address register The Host has read write 01E1 0034 HP...

Page 191: ...UHPI_HSTROBE high 5 ns 12 th HSTBH HDV Hold time host data valid after UHPI_HSTROBE high 2 ns Hold time UHPI_HSTROBE high after UHPI_HRDY low UHPI_HSTROBE should 13 th HRDYL HSTBH not be inactivated until UHPI_HRDY is active low otherwise HPI writes will not 2 ns complete properly 16 tsu HASL HSTBL Setup time UHPI_HAS low before UHPI_HSTROBE low 2 ns 17 th HSTBL HASH Hold time UHPI_HAS low after U...

Page 192: ...RDYV Delay time UHPI_HAS low to UHPI_HRDY valid 13 6 ten HSTBL HDLZ Enable time HD driven from UHPI_HSTROBE low 2 ns 7 td HRDYL HDV Delay time UHPI_HRDY low to HD valid 0 ns 8 toh HSTBH HDV Output hold time HD valid after UHPI_HSTROBE high 1 5 ns 14 tdis HSTBH HDHZ Disable time HD high impedance from UHPI_ HSTROBE high 12 ns For HPI Read Applies to conditions where data is already residing in HPID...

Page 193: ...ead operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur C UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2 UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE D The diagram above assumes UHPI_HAS has been pulled high ...

Page 194: ... www ti com A For correct operation strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle B UHPI_HSTROBE refers to the following logical operation on UHPI_HCS UHPI_HDS1 and UHPI_HDS2 NOT UHPI_HDS1 XOR UHPI_HDS2 OR UHPI_HCS Figure 6 68 UHPI Read Timing UHPI_HAS Used 194 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Docume...

Page 195: ...ead operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur C UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2 UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE D he diagram above assumes UHPI_HAS has been pulled high F...

Page 196: ...ww ti com A For correct operation strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle B UHPI_HSTROBE refers to the following logical operation on UHPI_HCS UHPI_HDS1 and UHPI_HDS2 NOT UHPI_HDS1 XOR UHPI_HDS2 OR UHPI_HCS Figure 6 70 UHPI Write Timing UHPI_HAS Used 196 Peripheral Information and Electrical Specifications Copyright 2008 2014 Texas Instruments Incorporated Submit Documen...

Page 197: ...ster 0 module 0 31 PSC1 0x01C1 0060 0x01E2 7060 PERRPR Power Error Pending Register 0x01C1 0068 0x01E2 7068 PERRCR Power Error Clear Register 0x01C1 0120 0x01E2 7120 PTCMD Power Domain Transition Command Register 0x01C1 0128 0x01E2 7128 PTSTAT Power Domain Transition Status Register 0x01C1 0200 0x01E2 7200 PDSTAT0 Power Domain 0 Status Register 0x01C1 0204 0x01E2 7204 PDSTAT1 Power Domain 1 Status...

Page 198: ...main Default Module State Auto Sleep Wake Only Number 0 Not Used 1 USB0 USB2 0 AlwaysON PD0 SwRstDisable 2 USB1 USB1 1 AlwaysON PD0 SwRstDisable 3 GPIO AlwaysON PD0 SwRstDisable 4 UHPI AlwaysON PD0 SwRstDisable 5 EMAC AlwaysON PD0 SwRstDisable 6 EMIFB Br 20 AlwaysON PD0 SwRstDisable 7 McASP0 McASP0 FIFO AlwaysON PD0 SwRstDisable 8 McASP1 McASP1 FIFO AlwaysON PD0 SwRstDisable 9 McASP2 McASP2 FIFO A...

Page 199: ...e SwRstDisable Asserted Off A module in the SwResetDisable state has its module reset asserted and it has its clock disabled After initial power on several modules come up in the SwRstDisable state Generally software is not expected to initiate this state Auto Sleep De asserted Off A module in the Auto Sleep state also has its module reset de asserted and its module clock disabled similar to the D...

Page 200: ...Map BYTE ADDRESS PRU0 PRU1 0x0000 0000 0x0000 0FFF PRU0 Instruction RAM PRU1 Instruction RAM Table 6 108 Programmable Real Time Unit Subsystem PRUSS Local Data Space Memory Map BYTE ADDRESS PRU0 PRU1 0x0000 0000 0x0000 01FF Data RAM 0 1 Data RAM 1 1 0x0000 0200 0x0000 1FFF Reserved Reserved 0x0000 2000 0x0000 21FF Data RAM 1 1 Data RAM 0 1 0x0000 2200 0x0000 3FFF Reserved Reserved 0x0000 4000 0x00...

Page 201: ...t 0x01C3 7010 0x01C3 7810 STALLCNT PRU Stall Count PRU Constant Table Block Index 0x01C3 7020 0x01C3 7820 CONTABBLKIDX0 Register 0 PRU Constant Table Programmable 0x01C3 7028 0x01C3 7828 CONTABPROPTR0 Pointer Register 0 PRU Constant Table Programmable 0x01C3 702C 0x01C3 782C CONTABPROPTR1 Pointer Register 1 PRU Internal General Purpose 0x01C37400 0x01C3747C 0x01C3 7C00 0x01C3 7C7C INTGPR0 INTGPR31...

Page 202: ...LECLR0 System Interrupt Enable Clear Register 0 0x01C3 4384 ENABLECLR1 System Interrupt Enable Clear Register 1 0x01C3 4400 0x01C3 4440 CHANMAP0 CHANMAP15 Channel Map Registers 0 15 0x01C3 4800 0x01C3 4808 HOSTMAP0 HOSTMAP2 Host Map Register 0 2 HOSTINTPRIIDX0 0x01C3 4900 0x01C3 4928 Host Interrupt Prioritized Index Registers 0 9 HOSTINTPRIIDX9 0x01C3 4D00 POLARITY0 System Interrupt Polarity Regis...

Page 203: ...ory accesses HSRTDX High Speed Real Time Data eXchange Advanced System Control Subsystem reset via debug Peripheral notification of debug events Cache coherent debug accesses Analysis Actions Stop program execution Generate debug interrupt Benchmarking with counters External trigger generation Debug state machine state transition Combinational and Sequential event generation Analysis Events Progra...

Page 204: ...ssor immediately prior to the execution of the selected instruction Imprecise breakpoints will halt the processor some number of cycles after the selected instruction depending on device conditions ARM Basic Debug Execution Control System Visibility Advanced Debug Global Start Global Stop Advanced System Control Subsystem reset via debug Peripheral notification of debug events Cache coherent debug...

Page 205: ...d with HWBPs Analysis Watch point with Data 8 watch points from ETM can be associated with a data comparator and ETM has total 4 data comparators Counters timers 3x32 bit 1 cycle 2 event External Event Trigger In 1 External Event Trigger Out 1 Internal Cross Triggering Signals One between ARM and DSP Address range for trace 4 Data qualification for trace 2 System events for trace control 20 Trace ...

Page 206: ...RTCK or RTCK is monitored by the emulator to gate TCK TMS I Test Mode Select Directs the next state of the IEEE 1149 1 test access port state machine TDI I Test Data Input Scan data input to the device TDO O Test Data Output Scan data output of the device EMU 0 I O Emulation 0 Channel 0 trigger HSRTDX 6 30 2 Scan Chain Configuration Parameters Table 6 115 shows the TAP configuration details requir...

Page 207: ...ate is shift ir Parameter The JTAG destination state is pause ir Parameter The bit length of the command is 6 Parameter The send data value is 0x00000007 Parameter The actual receive data is discarded Function Do a send only JTAG IR DR scan Parameter The route to JTAG shift state is shortest transition Parameter The JTAG shift state is shift dr Parameter The JTAG destination state is pause dr Para...

Page 208: ...Parameter The count of TCLK pulses is 10 Function Update the JTAG preamble and post amble counts Parameter The IR pre amble count is 0 Parameter The IR post amble count is 6 Parameter The DR pre amble count is 0 Parameter The DR post amble count is 1 Parameter The IR main count is 4 Parameter The DR main count is 1 The initial scan chain contains only the TAP router module The following steps must...

Page 209: ...value is 0xa3302108 Parameter The actual receive data is discarded Function Do a send only all ones JTAG IR DR scan Parameter The JTAG shift state is shift ir Parameter The JTAG destination state is run test idle Parameter The bit length of the command is 6 Parameter The send data value is all ones Parameter The actual receive data is discarded Function Wait for a minimum number of TCLK pulses Par...

Page 210: ...AG controllers from Texas Instruments actively drive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST When using this type of JTAG controller assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations 6 31 1 JTAG Peripheral Register Descripti...

Page 211: ...KH Pulse duration TCK high 16 ns 3 tw TCKL Pulse duration TCK low 16 ns 4 tc RTCK Cycle time RTCK 40 ns 5 tw RTCKH Pulse duration RTCK high 16 ns 6 tw RTCKL Pulse duration RTCK low 16 ns 7 tsu TDIV RTCKH Setup time TDI TMS TRST valid before RTCK high 4 ns 8 th RTCKH TDIV Hold time TDI TMS TRST valid after RTCK high 4 ns Table 6 119 Switching Characteristics Over Recommended Operating Conditions fo...

Page 212: ...s such as once per minute or once per day In addition the RTC can interrupt the CPU every time the calendar and time registers are updated or at programmable periodic intervals The real time clock RTC provides the following features 100 year calendar xx00 to xx99 Counts seconds minutes hours day of the week date month and year with leap year compensation Binary coded decimal BCD representation of ...

Page 213: ...The RTC has an internal oscillator buffer to support direct operation with a crystal The crystal is connected between pins RTC_XI and RTC_XO RTC_XI is the input to the on chip oscillator and RTC_XO is the output from the oscillator back to the crystal A crystal with 70k ohm max ESR is recommended Typical load capacitance values are 10 20 pF where the load capacitance is the series combination of C...

Page 214: ...s Register 0x01C2 302C ALARMDAY Alarm Days Register 0x01C2 3030 ALARMMONTH Alarm Months Register 0x01C2 3034 ALARMYEAR Alarm Years Register 0x01C2 3040 CTRL Control Register 0x01C2 3044 STATUS Status Register 0x01C2 3048 INTERRUPT Interrupt Enable Register 0x01C2 304C COMPLSB Compensation LSB Register 0x01C2 3050 COMPMSB Compensation MSB Register 0x01C2 3054 OSC Oscillator Register 0x01C2 3060 SCR...

Page 215: ...amily member has one of three prefixes X P or NULL e g XOMAPL137 Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes X TMDX through fully qualified production devices tools NULL TMDS Device development evolutionary flow X Experimental device that is ...

Page 216: ...he C674x DSP is an enhancement of the C64x and C67x DSPs with added functionality and an expanded instruction set SPRUFK5 TMS320C674x DSP Megamodule Reference Guide Describes the TMS320C674x digital signal processor DSP megamodule Included is a discussion on the internal direct memory access IDMA controller the interrupt controller the power down controller memory protection bandwidth management a...

Page 217: ...oblems with fellow engineers TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices 7 4 Trademarks DSP BIOS TMS320C6000 C6000 E2E are trademarks of Texas Instruments ARM926EJ S E...

Page 218: ...7 7 2 00 17 14 1 17 4 4 00 1 These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application For more information see these EIA JEDEC standards EIA JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air and JESD51 7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packa...

Page 219: ...ing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production ...

Page 220: ... finish options Finish options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes...

Page 221: ......

Page 222: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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