Texas Instruments OMAP-L137 EVM, User Manual

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OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014 www.ti.com
Table 6-102. Switching Characteristics for Host-Port Interface Cycles
(1) (2) (3)
No. PARAMETER MIN MAX UNIT
For HPI Write, UHPI_HRDY can go high ( not
ready ) for these HPI Write conditions;
otherwise, UHPI_HRDY stays low ( ready ):
Case 1 : Back-to-back HPIA writes (can be
either first or second half-word)
Case 2 : HPIA write following a PREFETCH
command (can be either first or second half-
word)
Case 3 : HPID write when FIFO is full or
flushing (can be either first or second half-
word)
Case 4 : HPIA write and Write FIFO not empty
For HPI Read, UHPI_HRDY can go high ( not
Delay time,
ready ) for these HPI Read conditions:
5 t
d(HSTBL-HRDYV)
UHPI_HSTROBE low to 12 ns
Case 1 : HPID read (with auto-increment) and
UHPI_HRDY valid
data not in Read FIFO (can only happen to
first half-word of HPID access)
Case 2 : First half-word access of HPID Read
without auto-increment
For HPI Read, UHPI_HRDY stays low (
ready )
for these HPI Read conditions:
Case 1 : HPID read with auto-increment and
data is already in Read FIFO (applies to either
half-word of HPID access)
Case 2 : HPID read without auto-increment
and data is already in Read FIFO (always
applies to second half-word of HPID access)
Case 3 : HPIC or HPIA read (applies to either
half-word access)
5a t
d(HASL-HRDYV)
Delay time, UHPI_HAS low to UHPI_HRDY valid 13
6 t
en(HSTBL-HDLZ)
Enable time, HD driven from UHPI_HSTROBE low 2 ns
7 t
d(HRDYL-HDV)
Delay time, UHPI_HRDY low to HD valid 0 ns
8 t
oh(HSTBH-HDV)
Output hold time, HD valid after UHPI_HSTROBE high 1.5 ns
14 t
dis(HSTBH-HDHZ)
Disable time, HD high-impedance from UHPI_ HSTROBE high 12 ns
For HPI Read. Applies to conditions where
data is already residing in HPID/FIFO:
Case 1 : HPIC or HPIA read
Delay time, Case 2 : First half-word of HPID read with
15 t
d(HSTBL-HDV)
15 ns
UHPI_HSTROBE low to HD valid auto-increment and data is already in Read
FIFO
Case 3 : Second half-word of HPID read with
or without auto-increment
For HPI Write, UHPI_HRDY can go high ( not
ready ) for these HPI Write conditions;
otherwise, UHPI_HRDY stays low ( ready ):
Delay time, Case 1 : HPID write when Write FIFO is full
18 t
d(HSTBH-HRDYV)
UHPI_HSTROBE high to (can happen to either half-word) 12 ns
UHPI_HRDY valid Case 2 : HPIA write (can happen to either half-
word)
Case 3 : HPID write without auto-increment
(only happens to second half-word)
(1) M=SYSCLK2 period (CPU clock frequency)/2 in ns.
(2) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(3) By design, whenever UHPI_HCS is driven inactive (high), HPI will drive UHPI_HRDY active (low).
192 Peripheral Information and Electrical Specifications
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