RF Core Data Memory
The Tx FIFO and Rx FIFO may be accessed though the SFR register
RFD
(0xD9). Data is written to the
Tx FIFO when writing to the
RFD
register. Data is read from the Rx FIFO when the
RFD
register is read. In
addition, there are separate read and write registers for each FIFO (
RFRXFRD
,
RFRXFWR
,
RFTXFRD
,
RFTXFWR
).
The Rx FIFO or Tx FIFO can be cleared by issuing CMD_RXFIFO_RESET or CMD_TXFIFO_RESET (see
), respectively. The contents of both FIFOs can be cleared by issuing
CMD_FIFO_RESET.
Four operations are defined to handle the four pointers:
•
Deallocate is setting SRP equal to RP. This should be done when the treatment of a packet that has
been read from the FIFO is finished.
•
Retry is setting RP equal to SRP. This is done to re-read a packet that has been read from the FIFO
previously.
•
Discard is setting WP equal to SWP. This is done to remove a packet that had been written to the
FIFO.
•
Commit is setting SWP equal to WP. This is done to confirm the writing of a packet to the FIFO and
making it available to be read out.
Using the register
RFFCFG
, it is possible to set up auto-commit and auto-deallocate for each of the FIFOs.
If auto-commit is enabled, SWP is set equal to WP each time a byte is written to the FIFO. If
auto-deallocate is enabled, SRP is set equal to RP each time a byte is read from the FIFO. By default,
auto-commit is enabled for the Tx FIFO and auto-deallocate is enabled for the Rx FIFO. This is also the
recommended setting. However, if packets that exceed the FIFO size are to be supported, auto-commit
must be enabled for the Rx FIFO and auto-deallocate for the Tx FIFO; see
and
for details. If auto-commit is disabled for the Tx FIFO, the MCU must issue a commit
command after writing a packet to the Tx FIFO, and if auto-deallocate is disabled for the Rx FIFO, the
MCU must issue a deallocate command after reading a packet from the Rx FIFO.
25.3.1.1 FIFO Status and Interrupts
The XREG registers
RFRXFLEN
and
RFTXFLEN
provide information on the amount of data in the FIFOs.
This is the number of bytes between SRP and WP, i.e., the number of bytes that is not free space in
. The register
RFFSTATUS
contains status bits for each of the FIFOs. FIFO empty is defined as
the length being 0, and FIFO full is defined as the length being 128. The amount of data between RP and
SWP is known as available data, and there is a status bit in the
RFFSTATUS
register telling whether there
is available data for each of the FIFOs.
An attempt to write to a full FIFO results in a FIFO overflow. The data written is then ignored and the
RXOVERF
or
TXOVERF
flag is set in the
RFERRF
register, causing an RFERR interrupt. An attempt to read
from a FIFO when no data is available results in a FIFO underflow. The value read is then zero, and the
RXUNDERF
or
TXUNDERF
flag is set in the
RFERRF
register, causing an RFERR interrupt.
Registers
RFTXFTHRS
and
RFRXFTHRS
are used to set threshold points for the Tx and Rx FIFOs,
respectively. Each FIFO has one status flag and two interrupt flags; when the amount of data in the FIFO
crosses the threshold, an interrupt flag is set. The FIFO status flags are available in
RFFSTATUS
, and the
interrupt flags are available in
RFIRQF0
.
When the amount of data in the FIFO is above the threshold, i.e.
RFxXFLEN
is greater than or equal to
RFxXFTHRS
, the status bit
xXDTHEX
of
RFFSTATUS
is 1, otherwise it is 0.
When data is written to the FIFO causing the FIFO threshold to be crossed, i.e.,
xXDTHEX
going from 0 to
1, the corresponding interrupt flag is set.
When data is read from the FIFO causing the FIFO threshold to be crossed, i.e.,
xXDTHEX
going from 1 to
0, the corresponding interrupt flag is set.
25.3.1.2 Command Register
The command register
RFST
can be used for sending commands to the FIFO. Commands in the range
0x80
–
0xFF are commands to the FIFO. Other commands are commands to the LLE; see
.
295
SWRU191C
–
April 2009
–
Revised January 2012
CC2541 Proprietary Mode Radio
Copyright
©
2009
–
2012, Texas Instruments Incorporated
