Texas Instruments CC2533 User Manual Download Page 168

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USART Registers

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•

UxGCR

, USART x generic control

•

UxDBUF

, USART x receive/transmit data buffer

•

UxBAUD

, USART x baud-rate control

U0CSR (0x86)

–

USART 0 Control and Status

Bit

Name

Reset

R/W

Description

MODE

R/W

USART mode select

SPI mode

UART mode

R/W

UART receiver enable. Note: Do not enable receive before UART is fully configured.

Receiver disabled

Receiver enabled

SLAVE

R/W

SPI master or slave mode select

SPI master

SPI slave

R/W0

UART framing error status. This bit is automatically cleared on a read of the

U0CSR

in the

U0CSR

No framing error detected

Byte received with incorrect stop-bit level

ERR

R/W0

UART parity error status. This bit is automatically cleared on a read of the

U0CSR

the

U0CSR

No parity error detected

Byte received with parity error

RX_BYTE

R/W0

Receive byte status. UART mode and SPI slave mode. This bit is automatically cleared when
reading

U0DBUF

; clearing this bit by writing 0 to it effectively discards the data in

U0DBUF

No byte received

Received byte ready

TX_BYTE

R/W0

Transmit byte status. UART mode and SPI master mode

Byte not transmitted

Last byte written to data-buffer register has been transmitted

ACTIVE

USART transmit/receive active status. In SPI slave mode, this bit equals slave select.

USART idle

USART busy in transmit or receive mode

168

USART

SWRU191C

–

April 2009

–

Revised January 2012

Submit Documentation Feedback

2009

–

2012, Texas Instruments Incorporated

Summary of Contents for CC2533

Page 1: ... Chip Solution for 2 4 GHz IEEE 802 15 4 and ZigBee Applications A CC2540 41 System on Chip Solution for 2 4 GHz Bluetooth low energy Applications User s Guide Literature Number SWRU191C April 2009 Revised January 2012 ...

Page 3: ... 39 2 3 6 Stack Pointer 39 2 4 Instruction Set Summary 39 2 5 Interrupts 43 2 5 1 Interrupt Masking 43 2 5 2 Interrupt Processing 47 2 5 3 Interrupt Priority 49 3 Debug Interface 53 3 1 Debug Mode 54 3 2 Debug Communication 54 3 3 Debug Commands 56 3 3 1 Debug Configuration 58 3 3 2 Debug Status 58 3 3 3 Hardware Breakpoints 59 3 4 Flash Programming 60 3 4 1 Lock Bits 60 3 5 Debug Interface and Po...

Page 4: ...2533 79 6 4 Flash DMA Trigger 79 6 5 Flash Controller Registers 79 7 I O Ports 81 7 1 Unused I O Pins 82 7 2 Low I O Supply Voltage 82 7 3 General Purpose I O 82 7 4 General Purpose I O Interrupts 82 7 5 General Purpose I O DMA 83 7 6 Peripheral I O 83 7 6 1 Timer 1 84 7 6 2 Timer 3 84 7 6 3 Timer 4 84 7 6 4 USART 0 85 7 6 5 USART 1 85 7 6 6 ADC 86 7 6 7 Operational Amplifier and Analog Comparator...

Page 5: ...es 116 9 9 4 Learning 117 9 9 5 Other Considerations 117 9 10 Timer 1 Interrupts 117 9 11 Timer 1 DMA Triggers 117 9 12 Timer 1 Registers 118 9 13 Accessing Timer 1 Registers as Array 123 10 Timer 3 and Timer 4 8 Bit Timers 125 10 1 8 Bit Timer Counter 126 10 2 Timer 3 Timer 4 Mode Control 126 10 2 1 Free Running Mode 126 10 2 2 Down Mode 126 10 2 3 Modulo Mode 126 10 2 4 Up Down Mode 126 10 3 Cha...

Page 6: ...AES Coprocessor 153 15 1 AES Operation 154 15 2 Key and IV 154 15 3 Padding of Input Data 154 15 4 Interface to CPU 154 15 5 Modes of Operation 154 15 6 CBC MAC 154 15 7 CCM Mode 155 15 8 AES Interrupts 157 15 9 AES DMA Triggers 157 15 10 AES Registers 157 16 Watchdog Timer 159 16 1 Watchdog Mode 160 16 2 Timer Mode 160 16 3 Watchdog Timer Register 160 17 USART 163 17 1 UART Mode 164 17 1 1 UART T...

Page 7: ...1 6 2 SETUP Transactions IDLE State 194 21 6 3 IN Transactions TX State 194 21 6 4 OUT Transactions RX State 195 21 7 Endpoints 1 5 195 21 7 1 FIFO Management 195 21 7 2 Double Buffering 196 21 7 3 FIFO Access 197 21 7 4 Endpoint 1 5 Interupts 197 21 7 5 Bulk Interrupt IN Endpoint 198 21 7 6 Isochronous IN Endpoint 198 21 7 7 Bulk Interrupt OUT Endpoint 198 21 7 8 Isochronous OUT Endpoint 198 21 8...

Page 8: ... Layer 228 23 8 Transmit Mode 229 23 8 1 TX Control 229 23 8 2 TX State Timing 229 23 8 3 TXFIFO Access 229 23 8 4 Retransmission 230 23 8 5 Error Conditions 230 23 8 6 TX Flow Diagram 230 23 8 7 Transmitted Frame Processing 232 23 8 8 Synchronization Header 232 23 8 9 Frame Length Field 232 23 8 10 Frame Check Sequence 232 23 8 11 Interrupts 233 23 8 12 Clear Channel Assessment 233 23 8 13 Output...

Page 9: ...upts 292 25 2 1 Interrupt Registers 292 25 3 RF Core Data Memory 293 25 3 1 FIFOs 294 25 3 2 DMA 297 25 3 3 RAM Based Registers 298 25 3 4 Variables in RAM Page 5 304 25 4 Bit Stream Processor 304 25 4 1 Whitening 304 25 4 2 CC2500 Compatible PN9 Whitening 305 25 4 3 CRC 306 25 4 4 Coprocessor Mode 308 25 5 Frequency and Channel Programming 309 25 6 Modulation Formats 309 25 7 Receiver 309 25 8 Pa...

Page 10: ...Stack Software www ti com z stack 360 27 6 BLE Stack Software 360 A Abbreviations 361 B Additional Information 365 B 1 Texas Instruments Low Power RF Web Site 366 B 2 Low Power RF Online Community 366 B 3 Texas Instruments Low Power RF Developer Network 366 B 4 Low Power RF eNewsletter 366 C References 367 Revision History 369 10 Contents SWRU191C April 2009 Revised January 2012 Submit Documentati...

Page 11: ...d Diagram 117 11 1 Sleep Timer Capture Example Using Rising Edge on P0_0 135 12 1 ADC Block Diagram 138 14 1 Basic Structure of the Random Number Generator 150 15 1 Message Authentication Phase Block B0 155 15 2 Authentication Flag Byte 155 15 3 Message Encryption Phase Block 156 15 4 Encryption Flag Byte 156 19 1 Analog Comparator 176 20 1 Block Diagram of the I2 C Module 178 20 2 I2 C Bus Connec...

Page 12: ...3 21 FFT of the Random Bytes 247 23 22 Histogram of 20 Million Bytes Generated With the RANDOM Instruction 247 23 23 Running a CSP Program 251 23 24 Example Hardware Structure for the R Register Access Mode 267 25 1 Mapping of Radio Memory to MCU XDATA Memory Space 294 25 2 FIFO Pointers 294 25 3 PN7 Whitening 305 25 4 CC2500 Compatible Whitening 306 25 5 CRC Module 307 25 6 Air Interface Packet F...

Page 13: ...ical Device 146 13 2 Values for A and B for a Typical Device When Using the Battery monitor for Temperature Monitoring 147 17 1 Commonly Used Baud Rate Settings for 32 MHz System Clock 166 20 1 Slave Transmitter Mode 181 20 2 Slave Receiver Mode 182 20 3 Master Transmitter Mode 184 20 4 Master Receiver Mode 185 20 5 Miscellaneous States 187 20 6 Clock Rates Defined at 32 MHz 188 21 1 USB Interrupt...

Page 14: ...t Tone 319 25 16 Interrupt and Counter Operation for Received Messages 320 25 17 Interrupt and Counter Operation for Received Messages 321 25 18 End of Receive Tasks 322 25 19 Interrupt and Counter Operation for Received ACK Packets 325 25 20 End of Transmit Tasks 326 25 21 Additional Reasons for End of Transmit on Clear Channel Tasks 327 25 22 Packet Sniffer Modes of Operation 331 25 23 XREG Regi...

Page 15: ... the IEEE 802 15 4 based standard protocols RemoTI network protocol TIMAC software and Z Stack software for ZigBee compliant solutions or on top of the proprietary SimpliciTI network protocol The usage is however not limited to these protocols alone The CC253x family is e g also suitable for 6LoWPAN and Wireless HART implementations Each chapter of this manual describes details of a module or peri...

Page 16: ...view and points out the differences regarding memory sizes and peripherals For a complete feature list of any of the devices see the corresponding data sheet Appendix C Table 0 1 CC253x Family Overview CC2530F32 F64 CC2540F128 CC2541F128 Feature CC2531F128 F256 CC2533F32 F64 F96 F128 F256 F256 F256 32 KB 64 KB 128 FLASH_SIZE 128 KB 256 KB 32 KB 64 KB 96 KB 128 KB 256 KB 128 KB 256 KB KB 256 KB 8 K...

Page 17: ...s In the register descriptions each register field is shown with a symbol R W indicating the access mode of the register field The register values are always given in binary notation unless prefixed by 0x which indicates hexadecimal notation Table 0 2 Register Bit Conventions SYMBOL ACCESS MODE R W Read write R Read only R0 Read as 0 R1 Read as 1 W Write only W0 Write as 0 W1 Write as 1 H0 Hardwar...

Page 19: ...ing blocks of the CC253x CC2540 41 device family For detailed device descriptions complete feature lists and performance numbers see the device specific data sheet Appendix C In order to provide easy access to relevant information the following subsections guide the reader to the different chapters in this guide Topic Page 1 1 Overview 20 1 2 Applications 25 19 SWRU191C April 2009 Revised January ...

Page 20: ...S AES ENCRYPTION AND DECRYPTION MEMORY ARBITER SFR IRAM XRAM PDATA 32 kHz RC OSC I O CONTROLLER DIGITAL ANALOG MIXED POWER MANAGEMENT CONTROLLER ON CHIP VOLTAGE REGULATOR POWER ON RESET BROWNOUT VDD 2 V 3 6 V DCOUPL SLEEP TIMER BATTERY MONITOR CC2533 ONLY USB USB PHY 1 KB FIFO SRAM DP DM CC2531 OP AMP ANALOG COMPARATOR Overview www ti com 1 1 Overview The block diagrams in Figure 1 1 and Figure 1 ...

Page 21: ...ODULATOR DEMODULATOR RECEIVE TRANSMIT FREQUENCY SYNTHESIZER SYNTH RF_P RF_N B0301 05 RADIO REGISTERS SFR Bus SFR Bus DS ADC AUDIO DC AES ENCRYPTION AND DECRYPTION MEMORY ARBITRATOR FLASH UNIFIED SFR IRAM XRAM PDATA SLEEP TIMER 32 kHz RC OSC I O CONTROLLER DIGITAL ANALOG MIXED ANALOG COMPARATOR USB_N USB_P Radio Arbiter Link Layer Engine www ti com Overview Figure 1 2 CC2540 Block Diagram The modul...

Page 22: ...d DECRYPTION WATCHDOG TIMER IRQ CTRL FLASH UNIFIED RF_P RF_N SYNTH MODULATOR POWER ON RESET BROWN OUT RADIO REGISTERS POWER MGT CONTROLLER SLEEP TIMER PDATA XRAM IRAM SFR XOSC_Q2 XOSC_Q1 DS ADC AUDIO DC DIGITAL ANALOG MIXED VDD 2 V 3 6 V DCOUPL ON CHIP VOLTAGE REGULATOR Link Layer Engine FREQUENCY SYNTHESIZER I 2 C DEMODULATOR RECEIVE TRANSMIT OP ANALOG COMPARATOR I O CONTROLLER 1 KB SRAM Radio Ar...

Page 23: ...nagement The digital core and peripherals are powered by a 1 8 V low dropout voltage regulator Chapter 26 Additionally the CC253x CC2540 41 contains a power management functionality that allows the use of different low power modes PM1 PM2 and PM3 for low power applications with a long battery life see Chapter 4 for more details Five different reset sources exist to reset the device see Chapter 5 f...

Page 24: ...r mode 2 PM2 The ADC Chapter 12 supports 7 bits 30 kHz bandwidth to 12 bits 4 kHz bandwidth of resolution DC and audio conversions with up to eight input channels Port 0 are possible The inputs can be selected as single ended or differential The reference voltage can be internal AVDD or a single ended or differential external signal The ADC also has a temperature sensor input channel The ADC can a...

Page 25: ...ily see the additional information sources in the following paragraphs The first step is to set up the development environment HW tools etc by purchasing a development kit see the device specific product Web site to find links to the relevant development kits The development kits come with an out of the box demo and information on how to set up the development environment install required drivers ...

Page 27: ...e core memory map instruction set and interrupts are described in the following subsections Topic Page 2 1 8051 CPU Introduction 28 2 2 Memory 28 2 3 CPU Registers 37 2 4 Instruction Set Summary 39 2 5 Interrupts 43 27 SWRU191C April 2009 Revised January 2012 8051 CPU Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 28: ...pace addresses 64 KB DATA A read write data memory space that can be directly or indirectly accessed by a single cycle CPU instruction This memory space addresses 256 bytes The lower 128 bytes of the DATA memory space can be addressed either directly or indirectly the upper 128 bytes only indirectly XDATA A read write data memory space access to which usually requires 4 5 CPU instruction cycles Th...

Page 29: ...rom SRAM improves performance and reduces power consumption The upper 32 KB of XDATA is a read only area called XBANK Any of the available 32 KB flash banks can be mapped in here This gives software access to the whole flash memory This area is typically used to store additional constant data Details about mapping of all 8051 memory spaces are given in Section 2 2 2 The memory map showing how the ...

Page 30: ...lash bank On 32 KB devices no flash memory can be mapped into the bank area Reads from this region return 0x00 on these devices To allow program execution from SRAM it is possible to map the available SRAM into the lower range of the bank area from 0x8000 through 0x8000 SRAM_SIZE 1 The rest of of the currently selected bank is still mapped into the address range from 0x8000 SRAM_SIZE through 0xFFF...

Page 31: ...des to be effective The Information Page is a 2 KB read only region that stores various device information Among other things it contains for IEEE 802 15 4 or Bluetooth low energy compliant devices a unique IEEE address from the TI range of addresses For CC253x this is a 64 bit IEEE address stored with least significant byte first at XDATA address 0x780C For CC2540 41 this is a 48 bit IEEE address...

Page 32: ... high DMA0CFGL 0xD4 DMA DMA channel 0 configuration address low DMA0CFGH 0xD5 DMA DMA channel 0 configuration address high DMAARM 0xD6 DMA DMA channel armed DMAREQ 0xD7 DMA DMA channel start request and status 0xAA Reserved 0x8E Reserved 0x99 Reserved 0xB0 Reserved 0xB7 Reserved 0xC8 Reserved P0IFG 0x89 IOC Port 0 interrupt status flag P1IFG 0x8A IOC Port 1 interrupt status flag P2IFG 0x8B IOC Por...

Page 33: ...alue low T1CC2H 0xDF Timer 1 Timer 1 channel 2 capture compare value high T1CNTL 0xE2 Timer 1 Timer 1 counter low T1CNTH 0xE3 Timer 1 Timer 1 counter high T1CTL 0xE4 Timer 1 Timer 1 control and status T1CCTL0 0xE5 Timer 1 Timer 1 channel 0 capture compare control T1CCTL1 0xE6 Timer 1 Timer 1 channel 1 capture compare control T1CCTL2 0xE7 Timer 1 Timer 1 channel 2 capture compare control T1STAT 0xA...

Page 34: ...oint interrupt mask flags U0CSR 0x86 USART 0 USART 0 control and status U0DBUF 0xC1 USART 0 USART 0 receive transmit data buffer U0BAUD 0xC2 USART 0 USART 0 baud rate control U0UCR 0xC4 USART 0 USART 0 UART control U0GCR 0xC5 USART 0 USART 0 generic control U1CSR 0xF8 USART 1 USART 1 control and status U1DBUF 0xF9 USART 1 USART 1 receive transmit data buffer U1BAUD 0xFA USART 1 USART 1 baud rate c...

Page 35: ...247 OBSSEL4 Observation output control register 4 0x6248 OBSSEL5 Observation output control register 5 0x6249 CHVER Chip version 0x624A CHIPID Chip identification 0x624B TR0 Test register 0 0x6260 DBGDATA Debug interface write data 0x6262 SRCRC Sleep reset CRC 0x6264 BATTMON Battery monitor 0x6265 IVCTRL Analog control register 0x6270 FCTL Flash control 0x6271 FADDRL Flash address low 0x6272 FADDR...

Page 36: ...DATA Memory Access The MPAGE register is used during instructions MOVX A Ri and MOVX Ri A MPAGE gives the 8 most significant address bits whereas the register Ri gives the 8 least significant bits In some 8051 implementations this type of XDATA access is performed using P2 to give the most significant address bits Existing software may therefore have to be adapted to make use of MPAGE instead of P...

Page 37: ... Valid settings depend on the flash size for the device Writing an invalid setting is ignored i e no update to MAP 2 0 is performed 32 KB version No value can be written Bank area is only used for running program code from SRAM See MEMCTR XMAP 64 KB version 0 1 96 KB version 0 2 128 KB version 0 3 256 KB version 0 7 2 3 CPU Registers This section describes the internal registers found in the CPU 2...

Page 38: ...follows and contains the carry flag auxiliary carry flag for BCD operations register select bits overflow flag and parity flag Two bits in the PSW are uncommitted and can be used as user defined status flags PSW 0xD0 Program Status Word Bit Name Reset R W Description 7 CY 0 R W Carry flag Set to 1 when the last arithmetic operation resulted in a carry during addition or borrow during subtraction o...

Page 39: ...ed to a different location not used for data storage SP 0x81 Stack Pointer Bit Name Reset R W Description 7 0 SP 7 0 0x07 R W Stack pointer 2 4 Instruction Set Summary The 8051 instruction set is summarized in Table 2 3 All mnemonics copyrighted Intel Corporation 1980 The following conventions are used in the instruction set summary Rn Register R7 R0 of the currently selected register bank Direct ...

Page 40: ...ncrement register 08 0F 1 2 INC direct Increment direct byte 05 2 3 INC Ri Increment indirect RAM 06 07 1 3 INC DPTR Increment data pointer A3 1 1 DEC A Decrement accumulator 14 1 1 DEC Rn Decrement register 18 1F 1 2 DEC direct Decrement direct byte 15 2 3 DEC Ri Decrement indirect RAM 16 17 1 3 MUL AB Multiply A and B A4 1 5 DIV A Divide A by B 84 1 5 DA A Decimal adjust accumulator D4 1 1 LOGIC...

Page 41: ...7 1 3 MOV Ri direct Move direct byte to indirect RAM A6 A7 2 5 MOV Ri data Move immediate data to indirect RAM 76 77 2 3 MOV DPTR data16 Load data pointer with a 16 bit constant 90 3 3 MOVC A A DPTR Move code byte relative to DPTR to accumulator 93 1 3 MOVC A A PC Move code byte relative to PC to accumulator 83 1 3 MOVX A Ri Move external RAM 8 bit address to A E2 E3 1 3 MOVX A DPTR Move external ...

Page 42: ...mediate to indirect and jump if not equal B6 B7 3 4 DJNZ Rn rel Decrement register and jump if not zero D8 DF 1 3 DJNZ direct rel Decrement direct byte and jump if not zero D5 3 4 NOP No operation 00 1 1 Boolean VARIABLE OPERATIONS CLR C Clear carry flag C3 1 1 CLR bit Clear direct bit C2 2 3 SETB C Set carry flag D3 1 1 SETB bit Set direct bit D2 2 3 CPL C Complement carry flag B3 1 1 CPL bit Com...

Page 43: ...ls have several events that can generate the interrupt request associated with that peripheral This applies to Port 0 Port 1 Port 2 Timer 1 Timer 2 Timer 3 Timer 4 DMA controller and Radio These peripherals have interrupt mask bits for each internal interrupt source in the corresponding SFR or XREG registers In order to enable any of the interrupts the following steps must be taken 1 Clear interru...

Page 44: ...n Interrupt Flag CPU Number Name Vector CPU 0 RF core error situation RFERR 0x03 IEN0 RFERRIE TCON RFERRIF 1 1 ADC end of conversion ADC 0x0B IEN0 ADCIE TCON ADCIF 1 2 USART 0 RX complete URX0 0x13 IEN0 URX0IE TCON URX0IF 1 3 USART 1 RX complete URX1 0x1B IEN0 URX1IE TCON URX1IF 1 4 AES encryption decryption complete ENC 0x23 IEN0 ENCIE S0CON ENCIF 5 Sleep Timer compare ST 0x2B IEN0 STIE IRCON STI...

Page 45: ...QF0 T1CCTL 0 4 IM TIMIF OVFIM T1STAT OVFIF T1STAT 4 0 T2IRQF T2IRQM TIMIF T3OVFIF T3CH0IF T3CH1IF 2 1 0 T3CCTL1 IM T3CCTL0 IM T3CTL OVFIM TIMIF T4OVFIF T4CH0IF T4CH1IF 5 4 3 T4CCTL1 IM T4CCTL0 IM T4CTL OVFIM PICTL P1ICON 0 1 P1IEN 1 PICTL P0ICON 0 1 0 P1IFG P0IFG PICTL P2ICON 0 1 2 P2IFG 4 0 P2IEN 4 0 P1 7 0 P0 7 0 P2 4 0 7 0 RFIRQM1 RFIRQF1 7 0 USB_DP P2IFG DPIF P2IEN 5 7 0 P0IEN 7 0 7 0 7 0 5 0 ...

Page 46: ...errupt enable 0 Interrupt disabled 1 Interrupt enabled 0 RFERRIE 0 R W RF core error interrupt enable 0 Interrupt disabled 1 Interrupt enabled IEN1 0xB8 Interrupt Enable 1 Bit Name Reset R W Description 7 6 00 R0 Reserved Read as 0 5 P0IE 0 R W Port 0 interrupt enable 0 Interrupt disabled 1 Interrupt enabled 4 T4IE 0 R W Timer 4 interrupt enable 0 Interrupt disabled 1 Interrupt enabled 3 T3IE 0 R ...

Page 47: ...errupt is enabled or disabled If the interrupt is enabled when an interrupt flag is set then on the next instruction cycle the interrupt is acknowledged by hardware forcing an LCALL to the appropriate vector address Interrupt response requires a varying amount of time depending on the state of the CPU when the interrupt occurs If the CPU is performing an interrupt service with equal or greater pri...

Page 48: ...hich is almost always the case one shot when interrupt request is initiated S0CON 0x98 Interrupt Flags 2 Bit Name Reset R W Description 7 2 0000 00 R W Reserved 1 ENCIF_1 0 R W AES interrupt ENC has two interrupt flags ENCIF_1 and ENCIF_0 Setting one of these flags requests interrupt service Both flags are set when the AES coprocessor requests the interrupt 0 Interrupt not pending 1 Interrupt pend...

Page 49: ...IF 0 R W DMA complete interrupt flag 0 Interrupt not pending 1 Interrupt pending IRCON2 0xE8 Interrupt Flags 5 Bit Name Reset R W Description 7 5 000 R W Reserved 4 WDTIF 0 R W Watchdog Timer interrupt flag 0 Interrupt not pending 1 Interrupt pending 3 P1IF 0 R W Port 1 interrupt flag 0 Interrupt not pending 1 Interrupt pending 2 UTX1IF 0 R W USART 1 TX interrupt flag 0 Interrupt not pending 1 Int...

Page 50: ...rupt group 0 priority control bit 1 see Table 2 7 Interrupt Priority Groups IP0 0xA9 Interrupt Priority 0 Bit Name Reset R W Description 7 6 00 R W Reserved 5 IP0_IPG5 0 R W Interrupt group 5 priority control bit 0 see Table 2 7 Interrupt Priority Groups 4 IP0_IPG4 0 R W Interrupt group 4 priority control bit 0 see Table 2 7 Interrupt Priority Groups 3 IP0_IPG3 0 R W Interrupt group 3 priority con...

Page 51: ...rupt Name 0 RFERR 16 RF 8 DMA 1 ADC 9 T1 2 URX0 10 T2 3 URX1 11 T3 Polling sequence 4 ENC 12 T4 5 ST 13 P0INT 6 P2INT 7 UTX0 14 UTX1 15 P1INT 17 WDT 51 SWRU191C April 2009 Revised January 2012 8051 CPU Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 53: ... debug data and debug clock respectively during debug mode These I O pins can be used as general purpose I O only while the device is not in debug mode Thus the debug interface does not interfere with any peripheral I O pins Topic Page 3 1 Debug Mode 54 3 2 Debug Communication 54 3 3 Debug Commands 56 3 4 Flash Programming 60 3 5 Debug Interface and Power Modes 60 3 6 Registers 62 53 SWRU191C Apri...

Page 54: ...em clock When running the debugger the value of CLKCONCMD CLKSPD should be set to 000 when CLKCONCMD OSC 0 or to 001 when CLKCONCMD OSC 1 3 2 Debug Communication The debug interface uses a SPI like two wire interface consisting of the P2 1 debug data and P2 2 debug clock pins Data is driven on the bidirectional debug data pin at the positive edge of the debug clock and data is sampled on the negat...

Page 55: ...arity of the figure not showing each individual bit change The direction is not explicitly indicated to the outside world but must be derived by the host from the command protocol Figure 3 3 Typical Command Sequence No Extra Wait for Response For commands that require a response there must be a small idle period between the command and the response to allow the pad to change direction After the mi...

Page 56: ...iver drives against the driver in the programmer until the programmer changes pad direction This duration should be minimized in a programmer implementation 3 3 Debug Commands The debug commands are shown in Table 3 1 Some of the debug commands are described in further detail in the following subsections The 3 least significant bits the Xs are don t care values Table 3 1 Debug Commands Additi Outp...

Page 57: ...es the next instruction from program memory and increments the program counter after execution The CPU must be in the halted state for this command to be run Input byte none Output byte The resulting accumulator register value after the instruction has been executed GET_BM 01100XXX 0 1 This command does the same thing as GET_PC except that it returns the memory bank It returns one byte where the 3...

Page 58: ...en the chip is halted The timers are also suspended during debug instructions When executing a STEP the timers receive exactly or as close as possible as many ticks as they would if the program were free running 0 Do not suspend timers 1 Suspend timers 0 0 Reserved Always write 0 3 3 2 Debug Status A debug status byte is read using the READ_STATUS command The format and description of this debug s...

Page 59: ...able 0 STACK_OVERFLOW 0 Stack overflow This bit indicates when the CPU writes to DATA memory space at address 0xFF which is possibly a stack overflow 0 No stack overflow 1 Stack overflow Table 3 4 Relation Between PCON_IDLE and PM_ACTIVE PCON_IDLE PM_ACTIVE Description 0 0 Chip in normal operation with CPU running if not halted 0 1 Chip in transition to start up from power mode 1 0 Chip in transit...

Page 60: ...rst byte contains the lock bit for page 0 bit 1 of the first byte contains the lock bit for page 1 and so on Bit 7 of the last byte in the flash is the DBGLOCK bit bit 127 in the structure Table 3 5 Flash Lock Protection Bit Structure Definition Bit Name Description 127 DBGLOCK Debug lock bit 0 Disable debug commands 1 Enable debug commands FLASH_PAGES 2 0 PAGELOCK FLASH_PAGES 2 0 Page lock bits T...

Page 61: ...ing in Idle mode and PM1 is not supported It is recommended to use active mode or another power mode when debugging 61 SWRU191C April 2009 Revised January 2012 Debug Interface Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 62: ...dependent CC2530 0xA5 CC2531 0xB5 CC2533 0x95 CC2540 0x8D CC2541 0x41 CHIPINFO0 0x6276 Chip Information Byte 0 Bit Name Reset R W Description 7 0 R0 Reserved Always 0 6 4 FLASHSIZE 2 0 Chip R Flash Size 001 32 KB 010 64 KB 011 128 KB for CC2533 011 96 KB dependent 100 256 KB 3 USB Chip R 1 if chip has USB 0 otherwise dependent 2 1 R1 Reserved Always 1 1 0 00 R0 Reserved Always 00 CHIPINFO1 0x6277 ...

Page 63: ...the power supply to modules to avoid static leakage power consumption and also by using clock gating and turning off oscillators to reduce dynamic power consumption Topic Page 4 1 Power Management Introduction 64 4 2 Power Management Control 65 4 3 Power Management Registers 66 4 4 Oscillators and Clocks 69 4 5 Timer Tick Generation 72 4 6 Data Retention 72 63 SWRU191C April 2009 Revised January 2...

Page 64: ...r the 32 kHz XOSC is running The system goes to active mode on reset an external interrupt or when the Sleep Timer expires PM3 The voltage regulator to the digital core is turned off None of the oscillators is running The system goes to active mode on reset or an external interrupt The POR is active in PM2 PM3 but the BOD is powered down which gives a limited voltage supervision If the supply volt...

Page 65: ...power consumption In PM3 all internal circuits that are powered from the voltage regulator are turned off basically all digital modules the only exceptions are interrupt detection and POR level sensing The internal voltage regulator and all oscillators are also turned off Reset POR or external and external I O port interrupts are the only functions that operate in this mode I O pins retain the I O...

Page 66: ...p the system is not executed until after the IEN0 EA bit has been set again later in the code If this functionality is not wanted the CLR EA instruction can be replaced by a NOP PUBLIC EnterSleepModeDisableInterruptsOnWakeup FUNCTION EnterSleepModeDisableInterruptsOnWakeup 0201H RSEG NEAR_CODE CODE NOROOT 2 EnterSleepModeDisableInterruptsOnWakeup MOV PCON 1 CLR EA RET 4 3 Power Management Register...

Page 67: ...trol Status Bit Name Reset R W Description 7 OSC32K_CALDIS 0 R 32 kHz RC oscillator calibration status SLEEPSTA OSC32K_CALDIS shows the current status of disabling of the 32 kHz RC calibration The bit is not set to the same value as SLEEPCMD OSC32K_CALDIS before the chip has been run on the 32 kHz RC oscillator 6 5 00 R Reserved 4 3 RST 1 0 XX R Status bit indicating the cause of the last reset If...

Page 68: ... Oscillator 32 kHz RC Oscillator CLKCONCMD OSC CLKCONCMD OSC32K SLEEPCMD OSC32K_CALDIS System Clock 32 kHz Clock Sleep Timer Watchdog Timer B0303 02 Power Management Registers www ti com Figure 4 1 Clock System Overview 68 Power Management and Clocks SWRU191C April 2009 Revised January 2012 Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 69: ...ystal oscillator is stable The 16 MHz RC oscillator consumes less power than the crystal oscillator but because it is not as accurate as the crystal oscillator it cannot be used for RF transceiver operation Two low frequency oscillators are present in the device 32 kHz crystal oscillator 32 kHz RC oscillator The 32 kHz XOSC is designed to operate at 32 768 kHz and provide a stable clock signal for...

Page 70: ...SC32K register bit can be written at any time but does not take effect before the 16 MHz RCOSC is the active system clock source When system clock is changed from the 16 MHz RCOSC to the 32 MHz XOSC CLKCONCMD OSC from 1 to 0 calibration of the 32 kHz RCOSC starts up and is performed once if the 32 kHz RCOSC is selected During calibration a divided version of the 32 MHz XOSC is used The result of t...

Page 71: ... any value but the effect is limited by the CLKCONCMD OSC setting i e if CLKCONCMD OSC 1 and CLKCONCMD TICKSPD 000 CLKCONSTA TICKSPD reads 001 and the real TICKSPD is 16 MHz 2 0 CLKSPD 001 R W Clock speed Cannot be higher than system clock setting given by the OSC bit setting Indicates current system clock frequency 000 32 MHz 001 16 MHz 010 8 MHz 011 4 MHz 100 2 MHz 101 1 MHz 110 500 kHz 111 250 ...

Page 72: ...25 MHz to 32 MHz It should be noted that if CLKCONCMD TICKSPD indicates a higher frequency than the system clock the actual prescaler value indicated in CLKCONSTA TICKSPD is the same as the system clock 4 6 Data Retention In power modes PM2 and PM3 power is removed from most of the internal circuitry However SRAM retains its contents and the content of internal registers is also retained in PM2 an...

Page 73: ...set values see register descriptions Watchdog Timer is disabled Clock loss detetector is disabled During reset the I O pins are configured as inputs with pullups P1 0 and P1 1 are inputs but do not have pullup pulldown In the CC2533 and CC2541 a watchdog reset can be generated immediately in software by writing the SRCRC FORCE_RESET bit to 1 see Section 4 3 for the register description In the othe...

Page 74: ... stops toggling a clock loss detector reset is generated within a certain maximum time out period The time out depends on which clock stops If the 32 kHz clock stops the time out period is 0 5 ms If the 32 MHz clock stops the time out period is 0 25 ms When the system comes up again from reset software can detect the cause of the reset by reading SLEEPSTA RST 1 0 After a reset the internal RC osci...

Page 75: ...530 CC2531 CC2540 CC2541 or 1024 bytes CC2533 each The flash controller has the following features 32 bit word programmable Page erase Lock bits for write protection and code security Flash page erase timing 20 ms Flash chip erase timing 20 ms Flash write timing 4 bytes 20 μs Topic Page 6 1 Flash Memory Organization 76 6 2 Flash Write 76 6 3 Flash Page Erase 78 6 4 Flash DMA Trigger 79 6 5 Flash C...

Page 76: ... start address This is the 16 MSBs of the 18 bit byte address 2 Set FCTL WRITE to 1 This starts the write sequence state machine 3 Write four times to FWDATA within 20 μs since the last time FCTL FULL became 0 if not first iteration LSB is written first FCTL FULL goes high after the last byte 4 Wait until FCTL FULL goes low The flash controller has started programming the 4 bytes written in step 3...

Page 77: ...tten 1 are ignored Only the bits written 0 are set to 0 whereas all bits 6 0xFFFb4FFFF 0xFFFb4b3b2b1b0 written 1 are ignored Only the bits written 0 are set to 0 whereas all bits 7 0xFFb5FFFFF 0xFFb5b4b3b2b1b0 written 1 are ignored Only the bits written 0 are set to 0 whereas all bits 8 0xFb6FFFFFF 0xFb6b5b4b3b2b1b0 written 1 are ignored Only the bits written 0 are set to 0 whereas all bits 9 0xb7...

Page 78: ...d by FADDRH 7 1 CC2530 CC2531 CC2540 CC2541 or FADDRH 6 0 CC2533 is erased when a page erase is initiated Note that if a page erase is initiated simultaneously with a page write i e FCTL WRITE is set to 1 the page erase is performed before the page write operation starts The FCTL BUSY bit can be polled to see when the page erase has completed Power mode 1 2 or 3 must not be entered while erasing a...

Page 79: ...ry the page to be erased is addressed with the register bits FADDRH 6 0 on CC2533 as opposed to FADDRH 7 1 on CC2530 CC2531 CC2540 The page lock bits are still placed in the upper 16 bytes of the last accessible flash page 6 4 Flash DMA Trigger The flash DMA trigger is activated when flash data written to the FWDATA register has been written to the specified location in the flash memory thus indic...

Page 80: ...onsumption is lower Note The value read always represents the current cache mode Writing a new cache mode starts a cache mode change request that may take several clock cycles to complete Writing to this register is ignored if there is a current cache change request in progress 1 WRITE 0 R W1 Write Start writing word at location given by FADDRH FADDRL The WRITE bit stays H0 at 1 until the write co...

Page 81: ...errupt capability The external interrupt capability is available on all 21 I O pins Thus external devices may generate interrupts if required The external interrupt feature can also be used to wake the device up from sleep mode power modes PM1 PM2 PM3 Topic Page 7 1 Unused I O Pins 82 7 2 Low I O Supply Voltage 82 7 3 General Purpose I O 82 7 4 General Purpose I O Interrupts 82 7 5 General Purpose...

Page 82: ...ding pin becomes an output When reading the port registers P0 P1 and P2 the logic values on the input pins are returned regardless of the pin configuration This does not apply during the execution of read modify write instructions The read modify write instructions are ANL ORL XRL JBC CPL INC DEC DJNZ MOV CLR and SETB Operating on a port register the following is true When the destination is an in...

Page 83: ... setting the appropriate PxSEL bits to 1 is required for the output signals on a digital I O pin to be controlled by the peripheral For peripheral inputs from digital I O pins this is optional PxSEL 1 overrides the pullup pulldown settings of a pin so to be able to control pullup pulldown with the PxINP bits the PxSEL bit should be set to 0 for that pin Note that peripheral units have two alternat...

Page 84: ...n move both USART 0 and USART 1 to the alternative 2 location P2SEL PRI1P1 and P2SEL PRI0P1 select the order of precedence when assigning several peripherals to Port 1 The Timer 1 channels have precedence when the former is set low and the latter is set high 7 6 2 Timer 3 PERCFG T3CFG selects whether to use alternative 1 or alternative 2 locations In Table 7 1 the Timer 3 signals are shown as the ...

Page 85: ...ART mode is selected and hardware flow control is disabled Timer 1 or Timer 3 has precedence to use ports P1 2 and P1 3 7 6 5 USART 1 The SFR register bit PERCFG U1CFG selects whether to use alternative 1 or alternative 2 locations In Table 7 1 the USART 1 signals are shown as follows UART RX RXDATA TX TXDATA RT RTS CT CTS SPI MI MISO MO MOSI C SCK SS SSN P2DIR PRIP0 selects the order of precedenc...

Page 86: ...APCFG register override the settings in P0SEL 7 7 Debug Interface Ports P2 1 and P2 2 are used for debug data and clock signals respectively These are shown as DD debug data and DC debug clock in Table 7 1 When in debug mode the debug interface controls the direction of these pins Pullup pulldown is disabled on these pins while in debug mode 7 8 32 kHz XOSC Input Ports P2 3 and P2 4 can be used to...

Page 87: ... register APCFG Analog peripheral I O configuration P0SEL Port 0 function select register P1SEL Port 1 function select register P2SEL Port 2 function select register P0DIR Port 0 direction register P1DIR Port 1 direction register P2DIR Port 2 direction register P0INP Port 0 input mode register P1INP Port 1 input mode register P2INP Port 2 input mode register P0IFG Port 0 interrupt status flag regi...

Page 88: ...ion 0 Alternative 1 location 1 Alternative 2 location 3 2 00 R W Reserved 1 U1CFG 0 R W USART 1 I O location 0 Alternative 1 location 1 Alternative 2 location 0 U0CFG 0 R W USART 0 I O location 0 Alternative 1 location 1 Alternative 2 location APCFG 0xF2 Analog Peripheral I O Configuration Bit Name Reset R W Description 7 0 APCFG 7 0 0x00 R W Analog Perpheral I O configuration APCFG 7 0 select P0 ...

Page 89: ...the same pins 0 Timer 1 has priority 1 Timer 4 has priority 3 PRI0P1 0 R W Port 1 peripheral priority control This bit determines the order of priority in the case when PERCFG assigns USART 0 and Timer 1 to the same pins 0 USART 0 has priority 1 Timer 1 has priority 2 SELP2_4 0 R W P2 4 function select 0 General purpose I O 1 Peripheral function 1 SELP2_3 0 R W P2 3 function select 0 General purpo...

Page 90: ... priority Timer 1 channels 2 3 11 1st priority Timer 1 channels 2 3 2nd priority USART 0 3rd priority USART 1 4th priority Timer 1 channels 0 1 5 0 R0 Reserved 4 0 DIRP2_ 4 0 0 0000 R W P2 4 to P2 0 I O direction 0 Input 1 Output P0INP 0x8F Port 0 Input Mode Bit Name Reset R W Description 7 0 MDP0_ 7 0 0x00 R W P0 7 to P0 0 I O input mode 0 Pullup pulldown see P2INP 0xF7 Port 2 input mode 1 3 stat...

Page 91: ...input port pin has an interrupt request pending the corresponding flag bit is set P1IFG 0x8A Port 1 Interrupt Status Flag Bit Name Reset R W Description 7 0 P1IF 7 0 0x00 R W0 Port 1 inputs 7 to 0 interrupt status flags When an input port pin has an interrupt request pending the corresponding flag bit is set P2IFG 0x8B Port 2 Interrupt Status Flag Bit Name Reset R W Description 7 6 00 R0 Reserved ...

Page 92: ...t configuration This bit selects the interrupt request condition for the low nibble of Port 1 inputs 0 Rising edge on input gives interrupt 1 Falling edge on input gives interrupt 0 P0ICON 0 R W Port 0 inputs 7 to 0 interrupt configuration This bit selects the interrupt request condition for all Port 0 inputs 0 Rising edge on input gives interrupt 1 Falling edge on input gives interrupt P0IEN 0xAB...

Page 93: ...6 0 SEL 6 0 000 0000 R W Select output signal on observation output 0 111 1011 123 rfc_obs_sig0 111 1100 124 rfc_obs_sig1 111 1101 125 rfc_obs_sig2 Others Reserved OBSSEL1 0x6244 Observation Output Control Register 1 Bit Name Reset R W Description 7 EN 0 R W Bit controlling observation output 1 on P1 1 0 Observation output disabled 1 Observation output enabled Note If enabled this overwrites the s...

Page 94: ...1 11 11101 125 rfc_obs_sig2 Others Reserved OBSSEL5 0x6248 Observation Output Control Register 5 Bit Name Reset R W Description 7 EN 0 R W Bit controlling the observation output 5 on P1 5 0 Observation output disabled 1 Observation output enabled Note If enabled this overwrites the standard GPIO behavior of P1 5 6 0 SEL 6 0 000 0000 R W Select output signal on observation output 5 111 1011 123 rfc...

Page 95: ...cally to transfer samples between ADC and memory etc Use of the DMA can also reduce system power consumption by keeping the CPU in a low power mode without having to wake up to move data to or from a peripheral unit see Section 4 1 1 for CPU low power mode Note that Section 2 2 3 describes the SFR registers that are not mapped into XDATA memory space The main features of the DMA controller are as ...

Page 96: ...ART transfer timer overflow The trigger event to be used by a DMA channel is set by the DMA channel configuration thus no knowledge of this is available until after the configuration has been read The DMA trigger events are listed in Table 8 1 In addition to starting a DMA transfer through the DMA trigger events the user software may force a DMA transfer to begin by setting the corresponding DMARE...

Page 97: ... Reached Transfer Count Block Transfer Mode Set Interrupt Flag 1 If IRQMASK 1 then 1 DMAIRQ DMAIFn IRCON DMAIF Repetitive Transfer Mode Setting 1 aborts all channels where the bit is set simultaneously I e setting 0x85 aborts channel 1 and channel 3 DMAARM ABORT DMAARMn DMAARM Yes No No No No No F0033 01 www ti com DMA Operation Figure 8 1 DMA Operation 97 SWRU191C April 2009 Revised January 2012 ...

Page 98: ...ation increment The source and destination addresses can be controlled to increment or decrement or not change Transfer mode The transfer mode determines whether the transfer should be a single transfer or a block transfer or repeated versions of these Byte or word transfers Determines whether each DMA transfer should be 8 bit byte or 16 bit word Interrupt mask An interrupt request is generated on...

Page 99: ...word 3 Transfer number of bytes words commanded by first byte word 2 transfers the length byte word and then as many bytes words as dictated by the length byte word 1 4 Transfer number of bytes words commanded by first byte word 3 transfers the length byte word and then as many bytes words as dictated by the length byte word 2 Figure 8 2 shows the VLEN options Figure 8 2 Variable Length VLEN Trans...

Page 100: ...channel can generate an interrupt to the processor This bit masks the interrupt 8 2 11 Mode 8 Setting This field determines whether to use 7 or 8 bits per byte for transfer length Only applicable when doing byte transfers 8 3 DMA Configuration Setup The DMA channel parameters such as address mode transfer mode and priority described in the previous section must be configured before a DMA channel c...

Page 101: ...ted 8 6 DMA Configuration Data Structure For each DMA channel the DMA configuration data structure consists of eight bytes The configuration data structure is described in Table 8 2 8 7 DMA Memory Access The DMA data transfer is affected by endian convention Note that the DMA descriptors follow big endian convention while the other registers follow little endian convention This must be accounted f...

Page 102: ...0 SRCADDR 7 0 DMA channel source address low 2 7 0 DESTADDR 15 8 DMA channel destination address high Note that flash memory is not directly writable 3 7 0 DESTADDR 7 0 DMA channel destination address low Note that flash memory is not directly writable 4 7 5 VLEN 2 0 Variable length transfer mode In word mode bits 12 0 of the first word are considered as the transfer length 000 Use LEN for transfe...

Page 103: ...each transfer 00 0 bytes words 01 1 byte word 10 2 bytes words 11 1 byte word 7 3 IRQMASK Interrupt mask for this channel 0 Disable interrupt generation 1 Enable interrupt generation on DMA channel done 7 2 M8 Mode of 8th bit for VLEN transfer length only applicable when WORDSIZE 0 and VLEN differs from 000 and 111 0 Use all 8 bits for transfer count 1 Use 7 LSB for transfer count 7 1 0 PRIORITY 1...

Page 104: ...bit is automatically cleared on completion DMAREQ 0xD7 DMA Channel Start Request and Status Bit Name Reset R W Description 7 5 000 R0 Reserved 4 DMAREQ4 0 R W1 H0 DMA transfer request channel 4 When set to 1 activate the DMA channel has the same effect as a single trigger event This bit is cleared when DMA transfer is started 3 DMAREQ3 0 R W1 H0 DMA transfer request channel 3 When set to 1 activat...

Page 105: ...omplete 1 DMA channel transfer complete interrupt pending 3 DMAIF3 0 R W0 DMA channel 3 interrupt flag 0 DMA channel transfer not complete 1 DMA channel transfer complete interrupt pending 2 DMAIF2 0 R W0 DMA channel 2 interrupt flag 0 DMA channel transfer not complete 1 DMA channel transfer complete interrupt pending 1 DMAIF1 0 R W0 DMA channel 1 interrupt flag 0 DMA channel transfer not complete...

Page 107: ... falling or any edge input capture Set clear or toggle output compare Free running modulo or up down counter operation Clock prescaler for divide by 1 8 32 or 128 Interrupt request generated on each capture compare and terminal count DMA trigger function Topic Page 9 1 16 Bit Counter 108 9 2 Timer 1 Operation 108 9 3 Free Running Mode 108 9 4 Modulo Mode 108 9 5 Up Down Mode 109 9 6 Channel Mode C...

Page 108: ...nter The counter produces an interrupt request when the terminal count value overflow is reached It is possible to start and halt the counter with T1CTL control register settings The counter is started when a value other than 00 is written to T1CTL MODE If 00 is written to T1CTL MODE the counter halts at its present value 9 2 Timer 1 Operation In general control register T1CTL is used to control t...

Page 109: ...en symmetrical output pulses are required with a period other than 0xFFFF and therefore allows implementation of center aligned PWM output applications The interrupt flag T1STAT OVFIF is set when the counter value reaches 0x0000 in the up down mode An interrupt request is generated if enabled see Section 9 10 for details Figure 9 3 Up Down Mode 9 6 Channel Mode Control The channel mode is set for ...

Page 110: ...are mode 6 or 7 defined by the T1CCTLn CMP bits where n is 1 or 2 as shown in Figure 9 4 The period of the PWM signal is determined by the setting in T1CC0 and the duty cycle is determined by T1CCn where n is the PWM channel 1 or 2 The timer free running mode may also be used In this case CLKCONCMD TICKSPD and the prescaler divider value in the T1CTL DIV bits set the period of the PWM signal The p...

Page 111: ...ggle output on compare 010 0 Set output on compare up clear on compare down in up down mode 011 0 In other modes than up down mode set output on compare clear on 0 011 0 Clear output on compare up set on compare down in up down mode 100 1 In other modes than up down mode clear output on compare set on 0 100 1 0 Clear when equal T1CC0 set when equal T1CCn 101 1 Set when equal T1CC0 clear when equal...

Page 112: ...Set When T1CCn 6 Set When T1CC0 Clear When T1CCn 2 Toggle Output on Compare 3 Set Output on Compare Up Clear on 0 T0311 01 Output Compare Mode www ti com Figure 9 4 Output Compare Modes Timer Free Running Mode 112 Timer 1 16 Bit Timer SWRU191C April 2009 Revised January 2012 Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 113: ... When T1CCn 6 Set When T1CC0 Clear When T1CCn 2 Toggle Output on Compare 3 Set Output on Compare Up Clear on 0 T0312 01 www ti com Output Compare Mode Figure 9 5 Output Compare Modes Timer Modulo Mode 113 SWRU191C April 2009 Revised January 2012 Timer 1 16 Bit Timer Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 114: ...T1CCn 2 Toggle Output on Compare 3 Set Output on Compare Up Clear on Compare Down T0313 01 4 Clear Output on Compare Up Set on Compare Down Output Compare Mode www ti com Figure 9 6 Output Compare Modes Timer Up Down Mode 114 Timer 1 16 Bit Timer SWRU191C April 2009 Revised January 2012 Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 115: ...frequency 32 000 kHz IR carrier frequency 38 kHz System clock period 0 00003125 ms IR carrier period 0 026315789 ms Timer prescaler 4 Timer period 0 000125 ms Ideal timer value 210 5263158 True timer value 211 True timer period 0 026375 ms True timer frequency 37 91469194 kHz Period error 59 21052632 ns Frequency error 85 30805687 Hz Frequency error 0 2245 The IRCTL IRGEN register bit enables IR g...

Page 116: ...gure 9 8 shows the example of Timer 3 being initialized to a 33 duty cycle T3CC0 3 T3CC1 Timer 1 has been initialized to 3 Figure 9 8 Modulated Waveform Example To achieve a period of space only T1CC1 should be set to 0x00 9 9 3 Non Modulated Codes To generate non modulated IR codes Timer 1 is used in modulo mode The period of the signal is given by T1CC0 and the pulse duration is given by T1CC1 T...

Page 117: ...et 9 10 Timer 1 Interrupts One interrupt vector is assigned to the timer An interrupt request is generated when one of the following timer events occurs Counter reaches terminal count value overflow or turns around zero Input capture event Output compare event The status register T1STAT contains the source interrupt flags for the terminal count value event and the five channel compare capture even...

Page 118: ...nter Low Bit Name Reset R W Description 7 0 CNT 7 0 0x00 R W Timer count low order byte Contains the low byte of the 16 bit timer counter Writing anything to this register results in the counter being cleared to 0x0000 and initializes all output pins of associated channels T1CTL 0xE4 Timer 1 Control Bit Name Reset R W Description 7 4 0000 R0 Reserved 3 2 DIV 1 0 00 R W Prescaler divider value Gene...

Page 119: ...est when set 5 3 CMP 2 0 000 R W Channel 0 compare mode select Selects action on output when timer value equals compare value in T1CC0 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare up clear on 0 100 Clear output on compare up set on 0 101 Reserved 110 Reserved 111 Initialize output pin CMP 2 0 is not changed 2 MODE 0 R W Mode Select Ti...

Page 120: ...2 0 is not changed 2 MODE 0 R W Mode Select Timer 1 channel 1 capture or compare mode 0 Capture mode 1 Compare mode 1 0 CAP 1 0 00 R W Channel 1 capture mode select 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on all edges T1CC1H 0xDD Timer 1 Channel 1 Capture Compare Value High Bit Name Reset R W Description 7 0 T1CC1 15 8 0x00 R W Timer 1 channel 1 capture compar...

Page 121: ...2 0 is not changed 2 MODE 0 R W Mode Select Timer 1 channel 2 capture or compare mode 0 Capture mode 1 Compare mode 1 0 CAP 1 0 00 R W Channel 2 capture mode select 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on all edges T1CC2H 0xDF Timer 1 Channel 2 Capture Compare Value High Bit Name Reset R W Description 7 0 T1CC2 15 8 0x00 R W Timer 1 channel 2 capture compar...

Page 122: ... 0 is not changed 2 MODE 0 R W Mode Select Timer 1 channel 3 capture or compare mode 0 Capture mode 1 Compare mode 1 0 CAP 1 0 00 R W Channel 3 capture mode select 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on all edges T1CC3H 0x62AD Timer 1 Channel 3 Capture Compare Value High Bit Name Reset R W Description 7 0 T1CC3 15 8 0x00 R W Timer 1 channel 3 capture compa...

Page 123: ... Reset R W Description 7 0 T1CC4 15 8 0x00 R W Timer 1 channel 4 capture compare value high order byte Writing to this register when T1CCTL4 MODE 1 compare mode causes the T1CC4 15 0 update to the written value to be delayed until T1CNT 0x0000 T1CC4L 0x62AE Timer 1 Channel 4 Capture Compare Value Low Bit Name Reset R W Description 7 0 T1CC4 7 0 0x00 R W Timer 1 channel 4 capture compare value low ...

Page 125: ...2 4 8 16 32 64 128 Interrupt request generated on each capture compare and terminal count event DMA trigger function Topic Page 10 1 8 Bit Timer Counter 126 10 2 Timer 3 Timer 4 Mode Control 126 10 3 Channel Mode Control 126 10 4 Input Capture Mode 127 10 5 Output Compare Mode 127 10 6 Timer 3 and Timer 4 Interrupts 127 10 7 Timer 3 and Timer 4 DMA Triggers 128 10 8 Timer 3 and Timer 4 Registers 1...

Page 126: ...ed An interrupt request is generated if enabled see Section 10 6 for details The timer down mode can generally be used in applications where an event timeout interval is required 10 2 3 Modulo Mode When the timer operates in modulo mode the 8 bit counter starts at 0x00 and increments at each active clock edge After the count has reached the period value held in register TxCC0 the counter is reset ...

Page 127: ...l edges on output pins are glitch free when operating in a given compare output mode For simple PWM use output compare modes 4 and 5 are preferred Writing to compare register TxCC0 or TxCC1 does not take effect on the output compare value until the counter value is 0x00 When the capture takes place the interrupt flag for the channel TIMIF TxCHnIF x is 3 or 4 n is the channel number is set An inter...

Page 128: ...re T3_CH1 Timer 3 channel 1 capture compare T4_CH0 Timer 4 channel 0 capture compare T4_CH0 Timer 4 channel 1 capture compare 10 8 Timer 3 and Timer 4 Registers T3CNT 0xCA Timer 3 Counter Bit Name Reset R W Description 7 0 CNT 7 0 0x00 R Timer count byte Contains the current value of the 8 bit counter T3CTL 0xCB Timer 3 Control Bit Name Reset R W Description 7 5 DIV 2 0 000 R W Prescaler divider v...

Page 129: ...ar on 0xFF 110 Clear output on compare set on 0x00 111 Initialize output pin CMP 2 0 is not changed 2 MODE 0 R W Mode Select Timer 3 channel 0 mode 0 Capture mode 1 Compare mode 1 0 CAP 1 0 00 R W Capture mode select 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both edges T3CC0 0xCD Timer 3 Channel 0 Capture Compare Value Bit Name Reset R W Description 7 0 VAL 7...

Page 130: ...F 110 Clear output on compare set on 0x00 111 Initialize output pin CMP 2 0 is not changed 2 MODE 0 R W Mode Select Timer 3 channel 1 mode 0 Capture mode 1 Compare mode 1 0 CAP 1 0 00 R W Capture mode select 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both edges T3CC1 0xCF Timer 3 Channel 1 Capture Compare Value Bit Name Reset R W Description 7 0 VAL 7 0 0x00 R...

Page 131: ...it Name Reset R W Description 7 0 R0 Reserved 6 IM 1 R W Channel 0 interrupt mask 5 3 CMP 2 0 000 R W Channel 0 compare output mode select Specified action occurs on output when timer value equals compare value in T4CC0 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare up clear on 0 100 Clear output on compare up set on 0 101 Set output on...

Page 132: ... 4 Channel 1 Capture Compare Value Bit Name Reset R W Description 7 0 VAL 7 0 0x00 R W Timer capture compare value channel 1 Writing to this register when T4CCTL1 MODE 1 compare mode causes the T4CC1 VAL 7 0 update to the written value to be delayed until T4CNT CNT 7 0 0x00 TIMIF 0xD8 Timer 1 3 4 Interrupt Mask Flag Bit Name Reset R W Description 7 0 R0 Reserved 6 OVFIM 1 R W Timer 1 overflow inte...

Page 133: ...tering power mode PM1 or PM2 The main features of the Sleep Timer are the following 24 bit timer up counter operating at 32 kHz clock rate 24 bit compare with interrupt and DMA trigger 24 bit capture Topic Page 11 1 General 134 11 2 Timer Compare 134 11 3 Timer Capture 134 11 4 Sleep Timer Registers 135 133 SWRU191C April 2009 Revised January 2012 Sleep Timer Submit Documentation Feedback Copyrigh...

Page 134: ...hen setting a new compare value the value should be at least 5 more than the current sleep timer value Otherwise the timer compare event may be lost The interrupt enable bit for the ST interrupt is IEN0 STIE and the interrupt flag is IRCON STIF When a timer compare event occurs the interrupt flag IRCON STIF is asserted In PM1 and PM2 the Sleep Timer compare event may be used to wake up the device ...

Page 135: ...es capture 11 4 Sleep Timer Registers The registers used by the Sleep Timer are ST2 Sleep Timer 2 ST1 Sleep Timer 1 ST0 Sleep Timer 0 STLOAD Sleep Timer load status STCC Sleep Timer capture control STCS Sleep Timer capture status STCV0 Sleep Timer capture value byte 0 STCV1 Sleep Timer capture value byte 1 STCV2 Sleep Timer capture value byte 2 ST2 0x97 Sleep Timer 2 Bit Name Reset R W Description...

Page 136: ... new compare value STCC 0x62B0 Sleep Timer Capture Control Bit Name Reset R W Description 7 5 000 R0 Reserved 4 3 PORT 1 0 11 R Port select Valid settings are 0 2 Capture is disabled when set to 3 i e an invalid setting is selected 2 0 PIN 2 0 111 Pin select Valid settings are 0 7 when PORT 1 0 is 0 or 1 0 5 when PORT 1 0 is 2 Capture is disabled when an invalid setting is selected STCS 0x62B1 Sle...

Page 137: ...des an analog multiplexer with up to eight individually configurable channels and a reference voltage generator Conversion results can be written to memory through DMA Several modes of operation are available Topic Page 12 1 ADC Introduction 138 12 2 ADC Operation 138 137 SWRU191C April 2009 Revised January 2012 ADC Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 138: ... can be used as ADC inputs In the following these port pins are referred to as the AIN0 AIN7 pins The input pins AIN0 AIN7 are connected to the ADC It is possible to configure the inputs as single ended or differential inputs In the case where differential inputs are selected the differential inputs consist of the input pairs AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 and AIN6 AIN7 Note that no negative supply...

Page 139: ...nnel For ADCCON2 SCH greater than or equal to 12 the sequence consists of the selected channel only 12 2 3 Single ADC Conversion In addition to this sequence of conversions the ADC can be programmed to perform a single conversion from any channel Such a conversion is triggered by writing to the ADCCON3 register The conversion starts immediately unless a conversion sequence is already ongoing in wh...

Page 140: ...ce Voltage The positive reference voltage for analog to digital conversions is selectable as either an internally generated voltage the AVDD5 pin an external voltage applied to the AIN7 input pin or a differential voltage applied to the AIN6 AIN7 inputs The accuracy of the conversion results depend on the stability and noise properties of the reference voltage Offset from the wanted voltage introd...

Page 141: ...been read the EOC bit remains high 0 Conversion not complete 1 Conversion completed 6 ST 0 R W1 Start conversion Read as 1 until conversion has completed H0 0 No conversion in progress 1 Start a conversion sequence if ADCCON1 STSEL 11 and no sequence is running 5 4 STSEL 1 0 11 R W Start select Selects the event that starts a new conversion sequence 00 External trigger on P2 0 pin 01 Full speed Do...

Page 142: ...ts ENOB setting 10 256 decimation rate 10 bits ENOB setting 11 512 decimation rate 12 bits ENOB setting 3 0 SCH 3 0 0000 R W Sequence channel select Selects the end of the sequence A sequence can either be from AIN0 to AIN7 SCH 7 or from differential input AIN0 AIN1 to AIN6 AIN7 8 SCH 11 For other settings only one conversions is performed When read these bits indicate the channel number on which ...

Page 143: ...te 12 bits ENOB 3 0 ECH 3 0 0000 R W Single channel select Selects the channel number of the single conversion that is triggered by writing to ADCCON3 0000 AIN0 0001 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AIN6 0111 AIN7 1000 AIN0 AIN1 1001 AIN2 AIN3 1010 AIN4 AIN5 1011 AIN6 AIN7 1100 GND 1101 Reserved 1110 Temperature sensor 1111 VDD 3 TR0 0x624B Test Register 0 Bit Name Reset R W Descr...

Page 145: ...ol the functionality of the battery monitor The battery monitor can also be used to do simple temperature monitoring by connecting it to the chip internal temperature sensor instead of the supply voltage The input is controlled using the MONMUX register Topic Page 13 1 Functionality and Usage of the Battery Monitor 146 13 2 Using the Battery Monitor for Temperature Monitoring 146 13 3 Battery Moni...

Page 146: ...GE 5 Disable the battery monitor BATTMON_PD 1 to avoid unnecessary current consumption 13 2 Using the Battery Monitor for Temperature Monitoring The battery monitor can also be used to do some simple temperature monitoring When the battery monitor is connected to the internal temperature sensor instead of the supply voltage AVDD5 see the description of MONMUX in Section 13 3 it can indicate whethe...

Page 147: ...stant for all devices but B is not Information that can be used to calculate B for a given chip is included in the chip s information page see Section 2 2 3 for info about the information page Example Find the BATTMON_VOLTAGE setting that tells whether the temperature is above or below 75 C 2 The closest setting is 16 which corresponds to 70 C see Table 13 1 By writing 16 to BATTMON_VOLTAGE an out...

Page 148: ...7 3 0 024 V 2 266 V 18 1 93 V 18 3 0 024 V 2 290 V 19 1 93 V 19 3 0 024 V 2 314 V 20 1 93 V 20 3 0 024 V 2 338 V 21 1 93 V 21 3 0 024 V 2 362 V 22 1 93 V 22 3 0 024 V 2 386 V 23 1 93 V 23 3 0 024 V 2 410 V 24 1 93 V 24 3 0 024 V 2 434 V 25 1 93 V 25 3 0 024 V 2 458 V 26 1 93 V 26 3 0 024 V 2 482 V 27 2 482 V 27 26 0 169 V 2 651 V 28 2 482 V 28 26 0 169 V 2 820 V 29 2 482 V 29 26 0 169 V 2 989 V 30...

Page 149: ...about the random number generator and its usage Topic Page 14 1 Introduction 150 14 2 Random Number Generator Operation 150 14 3 Random Number Generator Registers 151 149 SWRU191C April 2009 Revised January 2012 Random Number Generator Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 150: ...3 unrolling and the ADCCON1 RCTRL bits are automatically cleared when the operation has completed 14 2 2 Seeding The LFSR can be seeded by writing to the RNDL register twice Each time the RNDL register is written the 8 LSBs of the LFSR are copied to the 8 MSBs and the 8 LSBs are replaced with the new data byte that was written to RNDL For the CC253x when a random value is required the LFSR should ...

Page 151: ... High Byte Bit Name Reset R W Description 7 0 RNDH 7 0 0xFF R W Random value or CRC result input data high byte When written a CRC16 calculation is triggered and the data value written is processed starting with the MSB The value returned when reading from this register is the 8 MSBs of the LFSR When used for random number generation reading this register returns the 8 MSBs of the random number Wh...

Page 153: ... and CBC MAC modes Hardware support for CCM mode 128 bit key and IV nonce DMA transfer trigger capability Topic Page 15 1 AES Operation 154 15 2 Key and IV 154 15 3 Padding of Input Data 154 15 4 Interface to CPU 154 15 5 Modes of Operation 154 15 6 CBC MAC 154 15 7 CCM Mode 155 15 8 AES Interrupts 157 15 9 AES DMA Triggers 157 15 10 AES Registers 157 153 SWRU191C April 2009 Revised January 2012 A...

Page 154: ... the input output registers should be performed using direct memory access DMA When using DMA with the AES coprosessor two DMA channels must be used one for input data and one for output data The DMA channels must be initialized before a start command is written to ENCCS Writing a start command generates a DMA trigger and the transfer is started After each block is processed an interrupt is genera...

Page 155: ...string Note that l a is the length of a in octets b If 0 l a 216 28 then L a is the 2 octet encoding of l a The additional authentication data is appended to the A_Data length field L a The additional authentication blocks are padded with zeros until the last additional authentication block is full There is no restriction on the length of a AUTH DATA L a Authentication Data zero padding 4 The last...

Page 156: ...e command 9 The software calls a CFB or an OFB encryption on the authenticated data T The uploaded buffer contents stay unchanged M 16 or only its first M bytes stay unchanged the others being set to 0 M 16 The result is U which is used later 10 The software calls a CTR mode encryption immediately on the still padded message blocks It must reload the IV when the CTR value is any value but zero 11 ...

Page 157: ... M 16 The result is T 7 The software calls a CTR mode decryption immediately on the encrypted message blocks C Reloading the IV CTR is not necessary Reference Authentication Tag Generation This phase is identical to the authentication phase of CCM encryption The only difference is that the result is named MACTag instead of T Message Authentication Checking Phase The software compares T with MACTag...

Page 158: ...mand to be performed when a 1 is written to ST 00 Encrypt block 01 Decrypt block 10 Load key 11 Load IV nonce 0 0 R W1 Start processing command set by CMD Must be issued for each command or 128 bit block of data ST H0 Cleared by hardware ENCDI 0xB1 Encryption Input Data Bit Name Reset R W Description 7 0 DIN 7 0 0x00 R W Encryption input data ENCDO 0xB2 Encryption Output Data Bit Name Reset R W De...

Page 159: ...intervals The features of the Watchdog Timer are as follows Four selectable timer intervals Watchdog mode Timer mode Interrupt request generation in timer mode The WDT is configured as either a Watchdog Timer or as a timer for general purpose use The operation of the WDT module is controlled by the WDCTL register The Watchdog Timer consists of a 15 bit counter clocked by the 32 kHz clock source No...

Page 160: ... of the watchdog period the Watchdog Timer generates a reset signal for the system When the WDT has been enabled in watchdog mode it is not possible to change the mode by writing to the WDCTL MODE 1 0 bits and the timer interval value cannot be changed In watchdog mode the WDT does not produce interrupt requests 16 2 Timer Mode To start the WDT in timer mode the WDCTL MODE 1 0 bits must be set to ...

Page 161: ...tchdog mode 11 Timer mode 1 0 INT 1 0 00 R W Timer interval select These bits select the timer interval which is defined as a given number of 32 kHz oscillator periods Note that the interval can only be changed when the WDT is IDLE so the interval must be set at the same time as the timer is started 00 Clock period 32 768 1 s when running the 32 kHz XOSC 01 Clock period 8192 0 25 s 10 Clock period...

Page 163: ...tical function and are assigned to separate I O pins See Section 7 6 for I O configuration Topic Page 17 1 UART Mode 164 17 2 SPI Mode 165 17 3 SSN Slave Select Pin 166 17 4 Baud Rate Generation 166 17 5 USART Flushing 167 17 6 USART Interrupts 167 17 7 USART DMA Triggers 167 17 8 USART Registers 167 163 SWRU191C April 2009 Revised January 2012 USART Submit Documentation Feedback Copyright 2009 20...

Page 164: ...e transmission has been started hence a new data byte value can be loaded into the data buffer while the byte is being transmitted 17 1 2 UART Receive Data reception on the UART is initiated when a 1 is written to the UxCSR RE bit The UART then searches for a valid start bit on the RXDx input pin and sets the UxCSR ACTIVE bit high When a valid start bit has been detected the received byte is shift...

Page 165: ... SPI Master Operation A SPI byte transfer in master mode is initiated when the UxDBUF register is written The USART generates the SCK serial clock using the baud rate generator see Section 17 4 and shifts the provided byte from the transmit register onto the MOSI output At the same time the receive register shifts in the received byte from the MISO input pin The UxCSR ACTIVE bit goes high when the...

Page 166: ...be used to remove this information In SPI master mode the SSN pin is not used When the USART operates as a SPI master and a slave select signal is required by an external SPI slave device then a general purpose I O pin should be used to implement the slave select signal function in software 17 4 Baud Rate Generation An internal baud rate generator sets the UART baud rate when operating in UART mod...

Page 167: ... and the data buffer is offloaded The USART interrupt enable bits are found in the IEN0 and IEN2 registers The interrupt flags are located in the TCON and IRCON2 registers See Section 2 5 for details of these registers The interrupt enables and flags are summarized as follows Interrupt enables USART0 RX IEN0 URX0IE USART1 RX IEN0 URX1IE USART0 TX IEN2 UTX0IE USART1 TX IEN2 UTX1IE Interrupt flags U...

Page 168: ...ERR 0 R W0 UART parity error status This bit is automatically cleared on a read of the U0CSR register or bits in the U0CSR register 0 No parity error detected 1 Byte received with parity error 2 RX_BYTE 0 R W0 Receive byte status UART mode and SPI slave mode This bit is automatically cleared when reading U0DBUF clearing this bit by writing 0 to it effectively discards the data in U0DBUF 0 No byte ...

Page 169: ...line 0 Low start bit 1 High start bit U0GCR 0xC5 USART 0 Generic Control Bit Name Reset R W Description 7 CPOL 0 R W SPI clock polarity 0 Negative clock polarity 1 Positive clock polarity 6 CPHA 0 R W SPI clock phase 0 Data is output on MOSI when SCK goes from CPOL inverted to CPOL and data input is sampled on MISO when SCK goes from CPOL to CPOL inverted 1 Data is output on MOSI when SCK goes fro...

Page 170: ...us In SPI slave mode this bit equals slave select 0 USART idle 1 USART busy in transmit or receive mode U1UCR 0xFB USART 1 UART Control Bit Name Reset R W Description 7 FLUSH 0 R0 W1 Flush unit When set this event stops the current operation and returns the unit to the idle state 6 FLOW 0 R W UART hardware flow enable Selects use of hardware flow control with RTS and CTS pins 0 Flow control disabl...

Page 171: ... W Baud rate exponent value BAUD_E along with BAUD_M determines the UART baud rate and the SPI master SCK clock frequency U1DBUF 0xF9 USART 1 Receive Transmit Data Buffer Bit Name Reset R W Description 7 0 DATA 7 0 0x00 R W USART receive and transmit data When writing this register the data written is written to the internal transmit data register When reading this register the data from the inter...

Page 173: ...ollowing features Low offset Ideal for use in combination with the onboard ADC in sensor applications Topic Page 18 1 Description 174 18 2 Calibration 174 18 3 Clock Source 174 18 4 Registers 174 173 SWRU191C April 2009 Revised January 2012 Operational Amplifier Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 174: ... 18 4 Registers This section describes the registers for the operational amplifier A OPAMPMC CC2530 CC2531 0x61A6 CC2540 0x61AD Operational Amplifier Mode Control Bit Name Reset R W Description 7 2 0000 00 R W Reserved Always write 0000 00 1 0 MODE 00 R W Operational amplifier mode 00 and 01 Non chop mode Higher offset 500 µV but no chopper ripple Use in conjunction with Mode 10 if offset cancella...

Page 175: ...in the CC2530 CC2531 CC240 and CC2541 has the following features Low power operation Wake up source Topic Page 19 1 Description 176 19 2 Register 176 175 SWRU191C April 2009 Revised January 2012 Analog Comparator Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 176: ...ernally to the edge detector that controls P0IFG 5 This makes it possible to associate an I O interrupt with a rising falling edge on the comparator output When enabled the comparator remains active while in power mode 2 or 3 Thus it is possible to wake up from power mode 2 3 on a rising or falling edge on the comparator output Figure 19 1 Analog Comparator 19 2 Register This section describes the...

Page 177: ...emiconductor 7 bit device addressing modes General call START RESTART STOP Multi master transmitter receiver mode Slave receiver transmitter mode Standard mode up to 100 kbps and fast mode up to 400 kbps support Figure 20 1 shows the block diagram of the I2 C module On the CC2533 and CC2541 the I2 C module is connected to pins 2 and 3 and uses the P2 interrupt to the CPU Pins 2 and 3 can alternati...

Page 178: ... device is recognized by a unique address and can operate as either a transmitter or a receiver A device connected to the I2 C bus can be considered as the master or the slave when performing data transfers A master initiates a data transfer and generates the clock signal SCL Any device addressed by a master is considered a slave I2 C data is communicated using the serial data SDA pin and the seri...

Page 179: ...ata bit transferred The I2 C module operates with byte data Data is transferred MSB first as shown in Figure 20 3 The first byte after a START condition consists of a 7 bit slave address and the R W bit When R W 0 the master transmits data to a slave When R W 1 the master receives data from a slave The ACK bit is sent from the receiver after each byte on the ninth SCL clock Figure 20 3 I2 C Module...

Page 180: ... RESTART After a RESTART is issued the slave address is again sent out with the new data direction specified by the R W bit The RESTART condition is shown in Figure 20 6 Figure 20 6 I2 C Module Addressing Format With Repeated START Condition 20 1 4 I2 C Module Operating Modes The I2 C module can operate in master transmitter master receiver slave transmitter or slave receiver mode The modes are di...

Page 181: ... transmitter operation Table 20 1 Slave Transmitter Mode Status Application Software Response Code To I2CCFG Status of the Value of Next Action Taken by I2 C Hardware I2 C To From I2CDATA I2CSTAT STA STO SI AA STAC 0xA8 Own SLA R Load data byte X 0 0 0 Last data byte is transmitted and ACK is received has been or X 0 0 1 Data byte is transmitted ACK is received received ACK load data byte has been...

Page 182: ...rrupt is triggered from the master the I2 C module is automatically configured as a receiver and I2CCFG SI is set After the first data byte is received the interrupt flag I2CCFG SI is set again The I2 C module automatically acknowledges the received data While the I2CCFG SI flag is set the bus is stalled by holding SCL low When the master generates a STOP condition the I2CCFG STO flag is set If th...

Page 183: ...not ACK is returned addressed with or X 0 0 1 Data byteis received and ACK is returned general call read data byte address DATA has been received ACK returned 0x98 Previously Read data byte 0 0 0 0 Switched to not addressed SLV mode no addressed with recognition of own SLA or general call address own SLA or 0 0 0 1 Switched to not addressed SLV mode own SLA or DATA byte has read data byte general ...

Page 184: ...Status Application Software Response Code To I2CCFG Status of the Value of Next Action Taken by I2 C Hardware I2 C To From I2CDATA I2CSTAT STA STO SI AA STAC 0x08 A START Load SLA W X 0 0 X SLA W is transmitted condition has ACK is received been transmitted 0x10 A repeated Load SLA W X 0 0 X As for START condition 0x08 START or X 0 0 X SLA W is transmitted I2 C is switched to MST REC condition has...

Page 185: ...er Receiver Mode Status Application Software Response Code To I2CCFG Status of the Value of Next Action Taken by I2 C Hardware I2C To From I2CDATA I2CSTAT STA STO SI AA STAC 0x08 A START Load SLA R X 0 0 X SLA R is transmitted condition has ACK is received been transmitted 0x10 A repeated Load SLA R X 0 0 X As above START or X 0 0 X SLA W is transmitted I2 C is switched to MST TRX condition has lo...

Page 186: ...west binary value The master transmitter that lost arbitration switches to the slave receiver mode If two or more devices send identical first bytes arbitration continues on the subsequent bytes Figure 20 7 Arbitration Procedure Between Two Master Transmitters 20 1 5 I2 C Clock Generation and Synchronization The I2 C clock SCL is provided by the master on the I2 C bus When the I2 C module is in ma...

Page 187: ...shared with Port 2 inputs hence the interrupt routine must also handle Port 2 interrupts if they are enabled For an interrupt request to be generated IEN2 P2IE must be set to 1 When an interrupt request has been generated the CPU starts executing the ISR if there are no higher priority interrupts pending An interrupt is generated from the I2 C module when one of the 26 out of 27 possible I2 C comp...

Page 188: ... in master slave receive mode When not set AA 0 an acknowledge is returned when Data byte is received while in master slave receive mode 1 CR1 0 R W Clock rate bit 1 0 CR0 0 R W Clock rate bit 0 Table 20 6 Clock Rates Defined at 32 MHz Bit Frequency CR2 CR1 CR0 Clock Divided by kHz 0 0 0 123 256 0 0 1 144 244 0 1 0 165 192 0 1 1 197 160 1 0 0 33 960 1 0 1 267 120 1 1 0 533 60 1 1 1 Reserved N A I2...

Page 189: ...enable 1 SCLOE 0 R W SCL pin output enable 0 SDAOE 0 R W SDA pin output enable I2CIO 0x6235 GPIO Bit Name Reset R W Description 7 2 000 R0 Reserved 1 SCLD 0 R W SCL data value When I2CWC SCLOE is set reading SCLD reads the output register not the pin When I2CWC SCLOE is cleared reading SCLD reads the pin Writing SCLD writes to the output register 0 SDAD 0 R W SDA data value When I2CWC SDAOE is set...

Page 191: ...x C Standard USB nomenclature is used regarding IN and OUT I e IN is always into the host PC and OUT is out of the host Topic Page 21 1 USB Introduction 192 21 2 USB Enable 192 21 3 48 MHz USB PLL 192 21 4 USB Interrupts 193 21 5 Endpoint 0 193 21 6 Endpoint 0 Interrupts 193 21 7 Endpoints 1 5 195 21 8 DMA 199 21 9 USB Reset 199 21 10 Suspend and Resume 199 21 11 Remote Wake Up 199 21 12 USB Regis...

Page 192: ...ows a block diagram of the USB controller The USB PHY is the physical interface with input and output drivers The USB SIE is the serial interface engine which controls the packet transfer to from the endpoints The USB controller is connected to the rest of the system through the memory arbiter Figure 21 1 USB Controller Block Diagram 21 2 USB Enable The USB is enabled by setting USBCTRL USB_EN to ...

Page 193: ...cates that there has been a falling edge on the D USB data pin This is a resume event 21 5 Endpoint 0 Endpoint 0 EP0 is a bidirectional control endpoint and during the enumeration phase all communication is performed across this endpoint Before the USBADDR register has been set to a value other than 0 the USB controller is only able to communicate through endpoint 0 Setting the USBADDR register to...

Page 194: ...data packet is exactly 8 bytes long and is referred to as the setup packet In the setup stage of a control transfer EP0 is in the IDLE state The USB controller rejects the data packet if the setup packet is not 8 bytes Also the USB controller examines the contents of the setup packet to determine whether or not there is a data stage in the control transfer If there is a data stage EP0 switches sta...

Page 195: ...sfer The size of the data packet is kept in the USBCNT0 registers Note that this value is only valid when USBCS0 OUTPKT_RDY 1 EP0 switches to the IDLE state when the status stage has completed The status stage may fail if the DATA1 packet received is not a zero length data packet or if the USBCS0 SEND_STALL bit is set to 1 The USBCS0 SENT_STALL bit then is asserted and an EP0 interrupt is generate...

Page 196: ...r retransmissions double buffering can be used This allows two packets to be buffered in the FIFO in each direction This is highly recommended for isochronous endpoints which are expected to transfer one data packet every USB frame without any retransmission For an isochronous endpoint one data packet is sent received every USB frame However the data packet may be sent received at any time during ...

Page 197: ...lly when USBMAXO bytes have been read from the OUT FIFO The AutoClear feature is enabled by setting USBCSOH AUTOCLEAR 1 The AutoClear feature can be used to reduce the time the data packet occupies the OUT FIFO buffer and is typically used for bulk endpoints A complementary AutoSet feature is supported for IN endpoints When enabled the USBCSIL INPKT_RDY bit is set automatically when USBMAXI bytes ...

Page 198: ...ded and hence violates the double buffering strategy Thus when double buffering is used the USBPOW ISO_WAIT_SOF bit should be set to 1 to avoid this Setting this bit ensures that a loaded data packet is not sent until the next SOF token has been received The AutoSet feature typically is not used for isochronous endpoints because the packet size increases or decreases from frame to frame 21 7 7 Bul...

Page 199: ...d Resume The USB controller asserts USBCIF SUSPENDIF and enters suspend mode when the USB has been continuously idle for 3 ms provided that USBPOW SUSPEND_EN 1 IRCON2 P2IF is asserted if USBCIE SUSPENDIE is enabled and an interrupt request is generated if IEN2 P2IE 1 While in suspend mode only limited current can be sourced from the USB See the USB 2 0 Specification 3 for details about this To be ...

Page 200: ... reset signaling this bit is set to 1 2 RESUME 0 R W Drives resume signaling for remote wakeup According to the USB Specification the duration of driving resume must be at least 1 ms and no more than 15 ms It is recommended to keep this bit set for approximately 10 ms 1 SUSPEND 0 R Suspend mode entered This bit is only used when SUSPEND_EN 1 Reading the USBCIF register or asserting RESUME clears t...

Page 201: ...led 2 INEP2IE 1 R W IN endpoint 2 interrupt enable 0 Interrupt disbled 1 Interrupt enabled 1 INEP1IE 1 R W IN endpoint 1 interrupt enable 0 Interrupt disbled 1 Interrupt enabled 0 EP0IE 1 R W Endpoint 0 interrupt enable 0 Interrupt disbled 1 Interrupt enabled USBOIE 0x6209 Out Endpoints Interrupt Enable Mask Bit Name Reset R W Description 7 6 00 R W Reserved Always write 00 5 OUTEP5IE 1 R W OUT en...

Page 202: ...0 5 USBCTRL 0x620F USB Control Register Bit Name Reset R W Description 7 PLL_LOCKED 0 R PLL locked status 6 3 R0 Reserved 2 0 R W Reserved Always write 0 1 PLL_EN 0 R W 48 MHz USB PLL enable When this bit is set the 48 MHz PLL is started However the USB must not be accessed before the PLL has locked i e PLL_LOCKED is 1 This bit can only be set when USB_EN 1 Note The PLL must be disabled before exi...

Page 203: ...ted if the interrupt is enabled Set CLR_OUTPKT_RDY 1 to de assert this bit USBCSIL 0x6211 IN EP 1 5 Control and Status Low Bit Name Reset R W Description 7 R0 Reserved 6 CLR_DATA_TOG 0 R W Setting this bit resets the data toggle to 0 Thus setting this bit forces the next data packet H0 to be a DATA0 packet This bit is automatically cleared 5 SENT_STALL 0 R W This bit is set when a STALL handshake ...

Page 204: ...is bit is set when a STALL handshake has been sent An interrupt request OUT EP 1 5 is generated if the interrupt is enabled This bit must be cleared from firmware 5 SEND_STALL 0 R W Set this bit to 1 to make the USB controller reply with a STALL handshake when receiving OUT tokens Firmware must clear this bit to end the STALL condition It is not possible to stall an isochronous endpoint thus this ...

Page 205: ...n USBCSOL OUTPKT_RDY is set USBF0 0x6220 Endpoint 0 FIFO Bit Name Reset R W Description 7 0 USBF0 7 0 0x00 R W Endpoint 0 FIFO Reading this register unloads one byte from the EP0 FIFO Writing to this register loads one byte into the EP0 FIFO Note The FIFO memory for EP0 is used for both incoming and outgoing data packets USBF1 0x6222 Endpoint 1 FIFO Bit Name Reset R W Description 7 0 USBF1 7 0 0x0...

Page 206: ...0 0x00 R W Endpoint 5 FIFO register Reading this register unloads one byte from the EP5 OUT FIFO Writing to this register loads one byte into the EP5 IN FIFO 206 USB Controller SWRU191C April 2009 Revised January 2012 Submit Documentation Feedback Copyright 2009 2012 Texas Instruments Incorporated ...

Page 207: ...enever Timer 2 is running and an external 32 kHz XOSC should be used for accurate results The main features of Timer 2 are the following 16 bit timer up counter providing for example a symbol frame period of 16 μs 320 μs Adjustable period with accuracy of 31 25 ns 2 16 bit timer compare function 24 bit overflow count 2 24 bit overflow compare function Start of frame delimiter capture function Time...

Page 208: ...n to multiplexed registers T2M1 T2M0 with T2MSEL T2MSEL set to 000 the 16 bit timer halts at its current value and a delta counter starts counting The T2M0 register must be written before T2M1 The delta counter starts counting from the delta value written down to zero Once the delta counter reaches zero the 16 bit timer starts counting again The delta counter decrements at the same rate as the tim...

Page 209: ...RQF TIMER2_OVF_COMPARE2F are set to 1 regardless of the interrupt mask value 22 1 10 Capture Input Timer 2 has a timer capture function which captures the time when the start of frame delimiter SFD status in the radio goes high When the capture event occurs the current timer value is captured in the capture register The capture value can be read from registers T2M1 T2M0 if register T2MSEL T2MSEL i...

Page 210: ...eneral The timer can be started and stopped synchronously with the 32 kHz clock rising edge Note that this event is derived from a 32 kHz clock signal but is synchronous with the 32 MHz system clock and thus has a period approximately equal to that of the 32 kHz clock period Syncronous starting and stopping must not be attempted unless both the 32 kHz clock and 32 MHz XOSC are running and stable A...

Page 211: ... calculated value If a synchronous start is done without a previous synchronuous stop the timer is loaded with unpredictable values To avoid this do the first start of the timer asynchronously then enable synchronous mode for subsequent stops and starts The method for calculating the new Timer 2 value and overflow count value is given as follows Because the Timer 2 and Sleep Timer clocks are async...

Page 212: ... maximum value is given in terms of the number of Sleep Timer clock periods i e 32 kHz clock periods tST max 22 5 Timer 2 Registers The SFR registers associated with Timer 2 are listed in this section These registers are the following T2MSEL Timer 2 multiplexed register control T2M1 Timer 2 multiplexed count high T2M0 Timer 2 multiplexed count low T2MOVF2 Timer 2 multiplexed overflow count 2 T2MOV...

Page 213: ...gister selects the internal registers that are modified or read when accessing T2MOVF0 T2MOVF1 and T2MOVF2 000 t2ovf overflow counter 001 t2ovf_cap overflow capture 010 t2ovf_per overflow period 011 t2ovf_cmp1 overflow compare 1 100 t2ovf_cmp2 overflow compare 2 101 to 111 Reserved 3 0 R0 Reserved Read as 0 2 0 T2MSEL 0 R W The value of this register selects the internal registers that are modifie...

Page 214: ...his register with T2MSEL T2MOVFSEL set to 000 returns the latched value of t2ovf 15 8 T2MOVF2 0xA6 Timer 2 Multiplexed Overflow Register 2 Bit Name Reset R W Function No 7 0 T2MOVF2 0 R W Indirectly returns modifies bits 23 16 of an internal register depending on the T2MSEL T2MOVFSEL value Reading this register with T2MSEL T2MOVFSEL set to 000 returns the latched value of t2ovf 23 16 T2IRQF 0xA1 T...

Page 215: ... 0 T2IRQM 0xA7 Timer 2 Interrupt Mask CC253x CC2540 Bit Name Reset R W Function No 7 6 0 R0 Reserved Read as 0 5 TIMER2_OVF_COMPARE2M 0 R W Enables the TIMER2_OVF_COMPARE2 interrupt 4 TIMER2_OVF_COMPARE1M 0 R W Enables the TIMER2_OVF_COMPARE1 interrupt 3 TIMER2_OVF_PERM 0 R W Enables the TIMER2_OVF_PER interrupt 2 TIMER2_COMPARE2M 0 R W Enables the TIMER2_COMPARE2 interrupt 1 TIMER2_COMPARE1M 0 R ...

Page 216: ...g and stopping of timer happens at the first positive edge of the 32 kHz clock Read Section 22 4 for more details regarding timer start and stop 0 RUN 0 R W Write 1 to start timer write 0 to stop timer When read it returns the last written value T2EVTCFG 0x9C Timer 2 Event Configuration CC253x CC2540 Bit Name Reset R W Function No 7 0 R0 Reserved Read as 0 6 4 TIMER2_EVENT2_CFG 0 R W Selects the e...

Page 217: ...0 t2ovf_long_cmp1_event 1001 t2ovf_long_cmp2_event 1010 1110 Reserved 1111 No event 3 0 TIMER2_EVENT1_CFG 0 R W Selects the event that triggers a T2_EVENT1 pulse 0000 t2_per_event 0001 t2_cmp1_event 0010 t2_cmp2_event 0011 t2ovf_per_event 0100 t2ovf_cmp1_event 0101 t2ovf_cmp2_event 0110 Reserved 0111 No event 1000 t2ovf_long_cmp1_event 1001 t2ovf_long_cmp2_event 1010 1110 Reserved 1111 No event 21...

Page 219: ...mory Map 224 23 5 Frequency and Channel Programming 226 23 6 IEEE 802 15 4 2006 Modulation Format 226 23 7 IEEE 802 15 4 2006 Frame Format 228 23 8 Transmit Mode 229 23 9 Receive Mode 233 23 10 RXFIFO Access 243 23 11 Radio Control State Machine 245 23 12 Random Number Generation 247 23 13 Packet Sniffing and Radio Test Output Signals 248 23 14 Command Strobe CSMA CA Processor 249 23 15 Registers ...

Page 220: ...nthesizer FS generates the carrier wave for the RF signal The command strobe processor CSP processes all commands issued by the CPU It also has a short program memory of 24 bytes making it possible to automate CSMA CA algorithms The radio RAM holds a FIFO for transmit data TXFIFO and a FIFO for receive data RXFIFO Both FIFOs are 128 bytes long In addition the RAM holds parameters for frame filteri...

Page 221: ...ster has gone from a nonzero state to an all zero state 0 No interrupt pending 1 Interrupt pending 6 RXPKTDONE 0 R W0 A complete frame has been received 0 No interrupt pending 1 Interrupt pending 5 FRAME_ACCEPTED 0 R W0 Frame has passed frame filtering 0 No interrupt pending 1 Interrupt pending 4 SRC_MATCH_FOUND 0 R W0 Source match found 0 No interrupt pending 1 Interrupt pending 3 SRC_MATCH_DONE ...

Page 222: ... Read as 0 6 STROBEERR 0 R W0 A command strobe was issued at a time it could not be processed Triggered if trying to disable radio when already disabled or when trying to do a SACK SACKPEND or SNACK command when not in active RX 0 No interrupt pending 1 Interrupt pending 5 TXUNDERF 0 R W0 TXFIFO underflowed 0 No interrupt pending 1 Interrupt pending 4 TXOVERF 0 R W0 TXFIFO overflowed 0 No interrup...

Page 223: ...nterrupt enabled 1 SFD 0 R W SFD has been received or transmitted 0 Interrupt disabled 1 Interrupt enabled 0 ACT_UNUSED 0 R W Reserved 0 Interrupt disabled 1 Interrupt enabled RFIRQM1 0x61A4 RF Interrupt Masks Bit Name Reset R W Description 7 6 00 R0 Reserved Read as 0 5 CSP_WAIT 0 R W Execution continued after a wait instruction in CSP 0 Interrupt disabled 1 Interrupt enabled 4 CSP_STOP 0 R W CSP...

Page 224: ...NT provide information on the amount of data in the FIFOs The FIFO contents can be cleared by issuing SFLUSHRX and SFLUSHTX RFD 0xD9 RF Data Bit Name Reset R W Description 7 0 RFD 7 0 0x00 R W Data written to the register is written to the TXFIFO When reading this register data from the RXFIFO is read 23 3 DMA It is possible to use direct memory access DMA to move data between memory and the radio...

Page 225: ...2 0x6173 PAN_ID LE The PAN ID used during destination address filtering 0x616A 0x6171 EXT_ADD LE The IEEE extended address used during destination address filtering SOURCE ADDRESS MATCHING CONTROL 8 MSBs of the 24 bit mask that enables disables automatic pending 0x6169 SRCSHORTPENDEN2 for each of the 24 short addresses 0x6168 SRCSHORTPENDEN1 8 LSBs of the 24 bit mask that enables disables automati...

Page 226: ... The carrier frequency fC in MHz is given by fC 2394 FREQCTRL FREQ 6 0 MHz and is programmable in 1 MHz steps IEEE 802 15 4 2006 specifies 16 channels within the 2 4 GHz band They are numbered 11 through 26 and are 5 MHz apart The RF frequency of channel k is given by Equation 4 4 For operation in channel k the FREQCTRL FREQ register should therefore be set to FREQCTRL FREQ 11 5 k 11 23 6 IEEE 802...

Page 227: ... 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 8 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 9 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 10 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 11 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 12 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 13 0 1 1 0 0 0 0...

Page 228: ... one byte with value 0xA7 PHY Header The PHY header consists only of the frame length field The frame length field defines the number of bytes in the MPDU Note that the value of the frame length field does not include the frame length field itself It does however include the frame check sequence FCS even if this is inserted automatically by the hardware The frame length field is 7 bits long and ha...

Page 229: ...transmission and forces an RX calibration The SRFOFF command strobe Aborts ongoing transmission reception and forces the FSM to the IDLE state The STXON command strobe Aborts ongoing transmission and forces an RX calibration To enable the receiver after transmission with STXON the FRMCTRL1 SET_RXENMASK_ON_TX bit should be set This sets bit 6 in RXENABLE when STXON is executed When transmitting wit...

Page 230: ...nsmission of a packet is only possible if the packet has been completely transmitted i e a packet cannot be aborted and then be retransmitted If a different frame is to be transmitted issue an ISFLUSHTX strobe and then write the new frame to the TXFIFO 23 8 5 Error Conditions There are two error conditions associated with the TXFIFO Overflow happens when the TXFIFO is full and another byte write i...

Page 231: ...e multiple other activities such as frame reception RX FIFO access and acknowledgment transmission using SACK SACKPEND or AUTOACK or idle periods random backoffs This has no side effects on the state of the TX buffer The placement of the SFLUSHTX strobe in the diagram shows the latest point in time where this strobe can be executed If fewer special cases is desired it is always possible to use the...

Page 232: ...ows how the synchronization header relates to the IEEE 802 15 4 specification When the required number of preamble bytes has been transmitted the radio automatically transmits the 1 byte SFD The SFD is fixed and it is not possible to change this value from software 23 8 9 Frame Length Field When the SFD has been transmitted the modulator starts to read data from the TXFIFO It expects to find the f...

Page 233: ...XONCCA command strobes They are both available in the FSMSTAT1 register Note that the CCA signal is updated four clock cycles system clock after the RSSI_VALID signal has been set 23 8 13 Output Power Programming The RF output power is controlled by the 7 bit value in the TXPOWER register The device data sheet Appendix C shows typical output power and current consumption for recommended settings w...

Page 234: ...fter frame reception there is by default an interval of 192 μs where SFD detection is disabled This interval can be disabled by clearing FSMCTRL RX2RX_TIME_OFF 23 9 3 Received Frame Processing The radio integrates critical portions of the RX requirements in IEEE 802 15 4 2003 and 2006 in hardware This reduces the CPU interruption rate simplifies the software that handles frame reception and provid...

Page 235: ...hreshold prior to SFD detection See the register descriptions of MDMCTRL0 and MDMCTRL1 for available options and recommended settings 23 9 5 Frame Filtering The frame filtering function rejects nonintended frames as specified by 1 section 7 5 6 2 third filtering level In addition it provides filtering on The eight different frame types see the FRMFILT1 register The reserved bits in the frame contr...

Page 236: ...luded in the frame the FRMFILT0 PAN_COORDINATOR bit must be set and the source PAN ID must equal PAN_ID for the frame to be accepted Reserved frame types 4 5 6 and 7 are only accepted when FRMFILT1 ACCEPT_FT4TO7_RESERVED 1 default is 0 Length byte 9 The following operations are performed before the filtering begins with no effect on the frame data stored in the RXFIFO Bit 7 of the length byte is m...

Page 237: ...en rejected Tips and Tricks The following register settings must be configured correctly FRMFILT0 PAN_COORDINATOR must be set if the device is a PAN coordinator and cleared if not FRMFILT0 MAX_FRAME_VERSION must correspond to the supported version s of the IEEE 802 15 4 standard The local address information must be loaded into RAM To avoid completely the receiving of frames during energy detectio...

Page 238: ...e device as required by IEEE 802 15 4 1 This is wasteful in terms of power consumption because the polling device must keep its receiver enabled for a considerable period of time even if there are no frames for it By loading the destination addresses in the indirect frame queue into the source address table and enabling the AUTOPEND function the radio sets the pending bit in outgoing acknowledgmen...

Page 239: ...ters on read access A 7 bit value called SRCRESINDEX When no source address is present in the received frame or there is no match on the received source address Bits 6 0 011 1111 If there is a match on the received source address Bits 4 0 The index of the first entry i e the one with the lowest index number with a match 0 23 for short addresses or 0 11 for extended addresses Bit 5 0 if the match i...

Page 240: ... address replaces another while the receiver is active the corresponding enable bit should be turned off during the modification This prevents the RF Core from using a combination of old and new values because it only considers entries that are enabled throughout the whole source matching process The following measures can be taken to avoid the next received frame overwriting the results from sour...

Page 241: ... 23 15 Data in RXFIFO for Different Settings Field Descriptions The RSSI value is measured over the first eight symbols following the SFD The CRC_OK bit indicates whether the FCS is correct 1 or incorrect 0 When incorrect software is responsible for discarding the frame The correlation value is the average correlation value over the first eight symbols following the SFD SRCRESINDEX is the same val...

Page 242: ...g reception however only the last strobe has an effect No strobe SNACK incorrect FCS No acknowledgment transmission SACK Acknowledgment transmission with the frame pending bit cleared SACKPEND Acknowledgment transmission with the frame pending bit set Automatic Control AUTOACK When FRMFILT0 FRM_FILTER_EN and FRMCTRL0 AUTOACK are both enabled the radio determines automatically whether or not to tra...

Page 243: ...inters are readable in RXFIRST_PTR RXLAST_PTR and RXP1_PTR This can be useful if one wants to access quickly a certain byte within a frame without having to read out the entire frame first Note that when using this direct accessing no FIFO pointers are updated The ISFLUSHRX command strobe resets the RXFIFO resetting all FIFO pointers and clearing all counters status signals and sticky error condit...

Page 244: ...FOP 1 When the error occurs frame reception is halted The frames currently stored in the RXFIFO may be read out before the condition is cleared with the ISFLUSHRX strobe Note that rejected frames can generate RX overflow if the condition occurs before the frame is rejected RX underflow is indicated by the RFERRF RXUNDERF flag being set RX underflow is a serious error condition that should not occu...

Page 245: ...y the MAC software to calculate the LQI value This approach has the disadvantage that e g a narrowband interferer inside the channel bandwidth can increase the RSSI and thus the LQI value although the true link quality actually decreases The radio therefore also provides an average correlation value for each incoming frame based on the first eight symbols following the SFD This unsigned 7 bit valu...

Page 246: ...ll TX and ACK states SRFOFF or SRXON r xenable 0 TX shutdown 26 57 ACK 49 54 SFD wait 3 6 RX 7 13 Timeout 190 s m RXFIFO reset 16 Frame not for me SFD detected RX RX wait 14 Timeout 192 s or rx2rx_time_off 1 m Overflow Slotted ACK RX overflow 17 ACK delay 55 Unslotted ACK ACK calibration 48 Timeout x s depending on length byte of the received frame m F0036 01 Radio Control State Machine www ti com...

Page 247: ...57 0x1A 0x39 1 0 23 12 Random Number Generation The RF Core can generate random bits The chip should be in RX when generation of random bits is required One must also make sure that the chip has been in RX long enough for the transients to have died out A convenient way to do this is to wait for the RSSI valid signal to go high Single random bits from either the I or Q channel can be read from the...

Page 248: ...by the modulator is the same data that is output by the packet sniffer However if automatic CRC generation is enabled the packet sniffer does NOT output these 2 bytes Instead it replaces the CRC bytes with 0x8080 This value can never occur as the last two bytes of a received frame when automatic CRC checking is enabled and thus it provides a way for the receiver of the sniffed data to separate fra...

Page 249: ...Processor Bit Name Reset R W Description 7 0 INSTR 7 0 0xD0 R W Data written to this register is written to the CSP instruction memory Reading this register returns the CSP instruction currently being executed 23 14 1 Instruction Memory The CSP executes single byte program instructions which are read from a 24 byte instruction memory Writes to the instruction memory are sequential written through ...

Page 250: ...nd strobe instructions may be written to RFST while a program is being executed In this case the immediate instruction is executed before the instruction in the instruction memory which is executed once the immediate instruction has been completed During program execution reading RFST returns the current instruction being executed An exception to this is the execution of immediate command strobes ...

Page 251: ...i com Command Strobe CSMA CA Processor Figure 23 23 Running a CSP Program 23 14 7 Registers CSPROG N N Ranging From 0 to 23 0x61C0 N CSP Program Bit Name Reset R W Description 7 0 CSP_INSTR 0xD0 R Byte N of the CSP program memory CSPCTRL 0x61E0 CSP Control Bit Bit Name Reset R W Description 7 1 0000 000 R0 Reserved Read as 0 0 MCU_CTRL 0 R W CSP MCU control input 251 SWRU191C April 2009 Revised Ja...

Page 252: ... is decremented each time the MAC Timer overflows while the CSP program is running The SCP program stops when decremented to 0 Setting CSPT 0xFF prevents the register from being decremented 23 14 8 Instruction Set Summary This section gives an overview of the instruction set This is intended as a summary and definition of instruction opcodes See Section 23 14 9 for a description of each instructio...

Page 253: ...mact_event2 to go high and then continue execution INT 1 0 1 1 1 0 1 0 Generate an IRQ_CSP_MANINT Issues an IRQ_CSP_MANINT interrupt request LABEL 1 0 1 1 1 0 1 1 Set the next instruction as the start of a repeat loop Enters the address of the next instruction into the loop start register WAITX 1 0 1 1 1 1 0 0 Wait for MAC Timer to overflow X times where X is the value of register X Each time a MA...

Page 254: ... CSP program Reset PC 23 14 9 Instruction Set Definition There are 20 basic instruction types Furthermore the command strobe and immediate strobe instructions can each be divided into 16 subinstructions giving an effective number of 42 different instructions The following subsections describe each instruction in detail Note the following definitions are used in this section PC CSP program counter ...

Page 255: ... register is incremented by 1 An original value of 0xFF overflows to 0x00 Operation Y Y 1 Opcode 0xC1 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 1 23 14 9 6 INCX Function Increment X Description The X register is incremented by 1 An original value of 0xFF overflows to 0x00 Operation X X 1 Opcode 0xC0 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 23 14 9 7 INCMAXY Function Increment Y not greater than M Description The Y reg...

Page 256: ...nction Wait for X MAC Timer overflows Description Wait for MAC Timer to overflow X times where X is the value of register X Each time a MAC Timer overflow is detected the value in register X is decremented Program execution continues as soon as X 0 If X 0 when instruction is run no wait is performed and execution continues directly An IRQ_CSP_WAIT interrupt request is generated when execution cont...

Page 257: ...C 1 when number of MAC Timer overflows W Opcode 0x80 W W 0 31 7 6 5 4 3 2 1 0 1 0 0 W 23 14 9 13 WEVENT1 Function Wait until MAC Timer event 1 Description Wait until next MAC Timer event Program execution continues with the next instruction when the wait condition is true Operation PC PC while MAC Timer compare false PC PC 1 when MAC Timer compare true Opcode 0xB8 7 6 5 4 3 2 1 0 1 0 1 1 1 0 0 0 2...

Page 258: ...d in the following table Condition Description Function Code C 000 CCA is true CCA 1 001 Synchronization word SFD 1 received and still receiving packet or synchronization word transmitted and still transmitting packet 010 CPU control true CSPCTRL CPU_CTRL 1 011 Reserved 100 Register X 0 X 0 101 Register Y 0 Y 0 110 Register Z 0 Z 0 111 RSSI is valid RSSI_VALID 1 Operation PC LABEL when C XOR N tru...

Page 259: ...ription The SSTOP instruction stops the CSP program execution Operation Stop execution Opcode 0xD2 7 6 5 4 3 2 1 0 1 1 0 1 0 0 1 0 23 14 9 19 SNOP Function No operation Description Operation continues at the next instruction Operation PC PC 1 Opcode 0xD0 7 6 5 4 3 2 1 0 1 1 0 1 0 0 0 0 23 14 9 20 SRXON Function Enable and calibrate frequency synthesizer for RX Description The SRXON instruction ass...

Page 260: ...ription The STXONCCA instruction enables TX after calibration if CCA indicates a clear channel Operation STXONCCA Opcode 0xDA 7 6 5 4 3 2 1 0 1 1 0 1 1 0 1 0 23 14 9 23 SSAMPLECCA Function Sample the current CCA value to SAMPLED_CCA Description The current CCA value is written to SAMPLED_CCA in XREG Operation SSAMPLECCA Opcode 0xDB 7 6 5 4 3 2 1 0 1 1 0 1 1 0 1 1 23 14 9 24 SRFOFF Function Disable...

Page 261: ...de 0xDE 7 6 5 4 3 2 1 0 1 1 0 1 1 1 1 0 23 14 9 27 SACK Function Send acknowledge frame with pending field cleared Description The SACK instruction sends an acknowledge frame The instruction waits for the radio to acknowledge the command before executing the next instruction Operation SACK Opcode 0xD6 7 6 5 4 3 2 1 0 1 1 0 1 0 1 1 0 23 14 9 28 SACKPEND Function Send acknowledge frame with the pend...

Page 262: ...0xD4 7 6 5 4 3 2 1 0 1 1 0 1 0 1 0 0 23 14 9 31 SRXMASKBITCLR Function Clear bit in RXENABLE Description The SRXMASKBITCLR instruction clears bit 5 in the RXENABLE register Operation SRXMASKBITCLR Opcode 0xD5 7 6 5 4 3 2 1 0 1 1 0 1 0 1 0 1 23 14 9 32 ISSTOP Function Stop program execution Description The ISSTOP instruction stops the CSP program execution and the IRQ_CSP_STOP interrupt flag is ass...

Page 263: ...ET Function Set bit in RXENABLE Description The ISRXMASKBITSET instruction immediately sets bit 5 in the RXENABLE register Operation SRXMASKBITSET Opcode 0xE4 7 6 5 4 3 2 1 0 1 1 1 0 0 1 0 0 23 14 9 36 ISRXMASKBITCLR Function Clear bit in RXENABLE Description The ISRXMASKBITCLR instruction immediately clears bit 5 in the RXENABLE register Operation SRXMASKBITCLR Opcode 0xE5 7 6 5 4 3 2 1 0 1 1 1 0...

Page 264: ...PLED_CCA in XREG Operation SSAMPLECCA Opcode 0xEB 7 6 5 4 3 2 1 0 1 1 1 0 1 0 1 1 23 14 9 40 ISRFOFF Function Disable RX TX and frequency synthesizer Description The ISRFOFF instruction immediately disables RX TX and the frequency synthesizer Operation FFCTL_SRFOFF_STRB 1 Opcode 0xEF 7 6 5 4 3 2 1 0 1 1 1 0 1 1 1 1 23 14 9 41 ISFLUSHRX Function Flush RXFIFO buffer and reset demodulator Description...

Page 265: ...th the pending field set Description The ISACKPEND instruction immediately sends an acknowledge frame with the pending field set The instruction waits for the radio to receive and interpret the command before executing the next instruction Operation SACKPEND Opcode 0xE7 7 6 5 4 3 2 1 0 1 1 1 0 0 1 1 1 23 14 9 45 ISNACK Function Abort sending of acknowledge frame Description The ISNACK instruction ...

Page 266: ...x6198 RSSI RSSISTAT RXFIRST RXFIFOCNT 0x619C TXFIFOCNT RXFIRST_PTR RXLAST_PTR RXP1_PTR 0x61A0 TXFIRST_PTR TXLAST_PTR RFIRQM0 0x61A4 RFIRQM1 RFERRM MONMUX RFRND 0x61A8 MDMCTRL0 MDMCTRL1 FREQEST RXCTRL 0x61AC FSCTRL FSCAL1 FSCAL2 0x61B0 FSCAL3 AGCCTRL0 AGCCTRL1 AGCCTRL2 0x61B4 AGCCTRL3 ADCTEST0 ADCTEST1 ADCTEST2 0x61B8 MDMTEST0 MDMTEST1 DACTEST0 DACTEST1 0x61BC DACTEST2 ATEST PTEST0 PTEST1 0x61C0 CS...

Page 267: ...nded setting for lowest spurious emission 23 15 2 Register Access Modes The Mode column in Table 23 7 shows what kind of accesses are allowed for each bit The Description column gives the meaning of the different alternatives Table 23 7 Register Bit Access Modes Mode Description R Read W Write R0 Read constant zero R1 Read constant one W1 Only possible to write one W0 Only possible to write zero R...

Page 268: ... filtering algorithm 0 Frame filtering off FRMFILT0 6 1 FRMFILT1 7 1 and SRCMATCH 2 0 are don t care 1 Frame filtering on FRMFILT1 0x6181 Frame Filtering Bit Name Reset R W Description No 7 ACCEPT_FT_4TO7_RESERVED 0 R W Defines whether reserved frames are accepted or not Reserved frames have frame type 100 101 110 or 111 0 Reject 1 Accept 6 ACCEPT_FT_3_MAC_CMD 1 R W Defines whether MAC command fra...

Page 269: ... 24 short address table entries Optional safety feature To ensure that an entry in the source matching table is not used while it is being updated set the corresponding SHORT_ADDR_EN bit to 0 while updating SRCSHORTEN1 0x6184 Short Address Matching Bit Name Reset R W Description No 7 0 SHORT_ADDR_EN 15 8 0x00 R W The 15 8 part of the 24 bit word SHORT_ADDR_EN See previoius description of SRCSHORTE...

Page 270: ...E 0 The last two bytes of the frame CRC 16 field are stored in the RXFIFO The CRC check if any must be done manually Note that this setting does not influence acknowledgment transmission including AUTOACK 5 AUTOACK 0 R W Defines whether the radio automatically transmits acknowledge frames or not When autoack is enabled all frames that are accepted by address filtering have the acknowledge request ...

Page 271: ...MASK STXON Sets bit 6 in RXENMASK if SET_RXENMASK_ON_TX 1 SRFOFF Clears all bits in RXENMASK SRXMASKBITSET Sets bit 5 in RXENMASK SRXMASKBITCLR Clears bit 5 in RXENMASK RXENABLE can be modified directly by the CPU by accessing registers RXMASKSET and RXMASKCLR There might be conflicts between the CSP and CPU operations if both try to modify RXENMASK simultaneously To handle the case of simultaneou...

Page 272: ...R 5 TXUNDERF 4 TXOVERF 3 RXUNDERF 2 RXOVERF 1 RXABO 0 NLOCK FREQCTRL 0x618F Controls the RF Frequency Bit Name Reset R W Description No 7 0 R0 Read as zero 6 0 FREQ 6 0 0x0B R W Frequency control word 2405 MHz ƒRF ƒLO 2394 FREQ 6 0 MHz The frequency word in FREQ 6 0 is an offset value from 2394 The device supports the frequency range from 2394 MHz to 2507 MHz The usable settings for FREQ 6 0 are c...

Page 273: ... Appendix C for recommended values see also Section 23 8 13 TXCTRL 0x6191 Controls the TX Settings Bit Name Reset R W Description No 7 0 R0 Reserved 6 4 DAC_CURR 2 0 110 R W Change the current in the DAC 3 2 DAC_DC 1 0 10 R W Adjusts the dc level to the TX mixer 1 0 TXMIX_CURRENT 1 0 01 R W Transmit mixers core current current increases with increasing setting FSMSTAT0 0x6192 Radio Status Register...

Page 274: ...STXONCCA strobe is issued 2 LOCK_STATUS 0 R 1 when PLL is in lock otherwise 0 1 TX_ACTIVE 0 R Status signal active when FFCTRL is in one of the transmit states 0 RX_ACTIVE 0 R Status signal active when FFCTRL is in one of the receive states FIFOPCTRL 0x6194 FIFOP Threshold Bit Name Reset R W Description No 7 0 R0 Read as zero 6 0 FIFOP_THR 6 0 100 0000 R W Threshold used when generating FIFOP sign...

Page 275: ... 0 when RSSI CCA_THR or when receiving a frame 2 0 CCA_HYST 2 0 010 R W Sets the level of CCA hysteresis Unsigned values given in dB RSSI 0x6198 RSSI Status Register Bit Name Reset R W Description No 7 0 RSSI_VAL 7 0 0x80 R RSSI estimate on a logarithmic scale signed number in 2s complement Unit is 1 dB The offset to use in order to convert the register value into the real RSSI value can be found ...

Page 276: ...s offset of the last byte 1 byte in the RXFIFO RXP1_PTR 0x619F RXFIFO Pointer Bit Name Reset R W Description No 7 0 RXP1_PTR 7 0 0x00 R RAM address offset of the first byte of the first frame in the RXFIFO TXFIRST_PTR 0x61A1 TXFIFO Pointer Bit Name Reset R W Description No 7 0 TXFIRST_PTR 7 0 0x00 R RAM address offset of the next byte to be transmitted from the TXFIFO TXLAST_PTR 0x61A2 TXFIFO Poin...

Page 277: ...ements for SFD detection 0 The correlation value of one of the zero symbols of the preamble must be above the correlation threshold 1 The correlation value of one zero symbol of the preamble and both symbols in the SFD must be above the correlation threshold 4 0 CORR_THR 4 0 0x14 R W Demodulator correlator threshold value required before SFD search Threshold value adjusts how the receiver synchron...

Page 278: ...ption No 7 0 R0 Reserved Read as 0 6 VCO_CAPARR_OE 0 R W Override the calibration result with the value from VCO_CAPARR 5 0 5 0 VCO_CAPARR 5 0 10 0000 R W VCO capacitor array setting Programmed during calibration Override value when VCO_CAPARR_OE 1 FSCAL3 0x61B0 Tune Frequency Calibration Bit Name Reset R W Description No 7 0 R0 Reserved Read as 0 6 VCO_DAC_EN_OV 0 R W Enables the VCO DAC when 1 5...

Page 279: ...applied gain setting 00 0 dB gain reference level 01 3 dB gain 10 6 dB gain 11 9 dB gain 0 LNA_CURRENT_OE 0 R W Write 1 to override the AGC LNA current setting with the values above LNA1_CURRENT LNA2_CURRENT and LNA3_CURRENT AGCCTRL3 0x61B4 AGC Control Bit Name Reset R W Description No 7 0 R0 Reserved Read as 0 6 5 AGC_SETTLE_WAIT 1 0 01 R W Time for AGC to wait for analog gain to settle after a g...

Page 280: ...DCTEST2 0x61B7 ADC Tuning Bit Name Reset R W Description No 7 0 R0 Reserved Read as 0 6 5 ADC_TEST_MODE 00 R W Test mode to enable output of ADC data from demodulator When enabled raw ADC data is clocked out on the GPIO pins 00 Test mode disabled 01 Data from both I and Q ADCs is output data rate 76 MHz 10 Data from I ADC is output Two and two ADC samples grouped data rate 38 MHz 11 Data from Q AD...

Page 281: ...e of operation 00 The input signal to the dc blocker is passed on to the output without any attempt to remove dc 01 Enable dc cancellation Normal operation 10 Freeze estimates of dc when sync is found Start estimating dc again when searching for the next frame 11 Reserved MDMTEST1 0x61B9 Test Register for Modem Bit Name Reset R W Description No 7 5 000 R0 Reserved Read as 0 4 MOD_IF 0 R W 0 Modula...

Page 282: ...1 bits 7 1 00 1000 bits 8 2 And so on If an invalid setting is chosen then the DAC outputs only zeros minimum value DACTEST2 0x61BC DAC Test Setting Bit Name Reset R W Description No 7 3 0010 1 R0 Reserved 2 0 DAC_SRC 2 0 000 R W The TX DAC s data source is selected by DAC_SRC according to 000 Normal operation from modulator 001 The DAC_I_O and DAC_Q_O override values 010 ADC data after decimation...

Page 283: ...NA mixer PD modes 00 Power up 01 LNA off mixer regulator on 10 LNA mixer off regulator on 11 PD When PD_OVERRIDE 1 1 TXMIX_PD 0 R W Transmit mixer power down signal when PD_OVERRIDE 1 0 AAF_PD 0 R W Antialiasing filter power down signal when PD_OVERRIDE 1 PTEST1 0x61BF Override Power Down Register Bit Name Reset R W Description No 7 4 0000 R0 Reserved Read as 0 3 PD_OVERRIDE 0 R W Override enablin...

Page 284: ... 0010 ffctrl_fifo Pin is high when one or more bytes are in the RXFIFO Low during RXFIFO overflow 01 0011 ffctrl_fifop Pin is high when the number of bytes in the RXFIFO exceeds the programmable threshold or at least one complete frame is in the RXFIFO Also high during RXFIFO overflow Not to be confused with the FIFOP exception 01 0100 packet_done A complete frame has been received I e the number ...

Page 285: ...R0 Reserved Always read as 0 5 4 DAC_CURR_CTRL 01 R W Controls bias current to DAC 00 100 IVREF 0 IREF bias 01 60 IVREF 40 IREF bias 10 40 IVREF 60 IREF bias 11 0 IVREF 100 IREF bias 3 LODIV_BIAS_CTRL 0 R W Controls bias current to LODIV 1 PTAT bias 0 IVREF bias 2 TXMIX_DC_CTRL 0 R W Controls dc bias in TXMIX 1 0 PA_BIAS_CTRL 11 R W Controls bias current to PA 00 IREF bias 01 IREF and IVREF bias 1...

Page 287: ... to access the radio directly The application interacts with the radio by sending API commands to the stack The TI BLE stack with documentation is available at www ti com blestack The CC2541 may also be run in proprietary mode see Chapter 25 for a description of the operation in that case Topic Page 24 1 Registers 288 287 SWRU191C April 2009 Revised January 2012 CC2540 CC2541 Bluetooth low energy ...

Page 288: ... which observable signal from rf_core is to be muxed out to rfc_obs_sigs 0 00 0000 0 Constant value 00 0001 1 Constant value 00 1001 TX active 00 1010 RX_active 11 0000 High from when receiver has found access address until packet is finished low otherwise 11 0001 High from the access address has been transmitted until end of packet low otherwise Other values reserved RFC_OBS_CTRL1 0x61AF RF Obser...

Page 289: ...r has found access address until packet is finished low otherwise 11 0001 High from the access address has been transmitted until end of packet low otherwise Other values reserved ATEST 0x61A9 Analog Test Control Bit Name Reset R W Description 7 6 00 R0 Reserved Read as 0 5 0 ATEST_CTRL 5 0 00 0000 R W Controls the analog test mode 00 0000 Disabled 00 0001 Enables the temperature sensor see also t...

Page 291: ...ed RAM which holds the 128 byte transmit and receive FIFO This chapter describes the proprietary mode operation of the CC2541 devices and features in the LLE program For Bluetooth low energy operation see Chapter 24 Topic Page 25 1 RF Core 292 25 2 Interrupts 292 25 3 RF Core Data Memory 293 25 4 Bit Stream Processor 304 25 5 Frequency and Channel Programming 309 25 6 Modulation Formats 309 25 7 R...

Page 292: ...RFERR interrupt interrupt 0 and the RF interrupt interrupt 12 with the following functions RFERR Error situations in the radio are signaled using this interrupt RF Interrupts coming from normal operation are signaled using this interrupt The RF interrupt vector combines the interrupts in RFIF Note that these RF interrupts are rising edge triggered Thus an interrupt is generated when e g the SFD st...

Page 293: ... addresses 6 and 7 4 Free for MCU use 5 Additional RAM based registers Reserved for LLE 6 Rx FIFO Tx FIFO for Rx with auto ACK ACK payload FIFO for addresses 7 0 and 1 The active memory page is selected in register RFRAMCFG PRE The selected page is accessible at XDATA addresses 0x6000 0x607F The Rx FIFO page page 6 is also accessible at XDATA addresses 0x6080 0x60FF The Tx FIFO page page 7 is also...

Page 294: ...flow detection and flushing of last entry or the entire FIFO The Rx and Tx FIFOs are fundamentally two similar modules Each FIFO has four pointers the write pointer WP the read pointer RP the start of packet write pointer SWP and the start of packet read pointer SRP WP and RP give the index in the FIFO where the next byte is to be written and read respectively SWP is used to indicate the start of ...

Page 295: ... 1 FIFO Status and Interrupts The XREG registers RFRXFLEN and RFTXFLEN provide information on the amount of data in the FIFOs This is the number of bytes between SRP and WP i e the number of bytes that is not free space in Figure 25 2 The register RFFSTATUS contains status bits for each of the FIFOs FIFO empty is defined as the length being 0 and FIFO full is defined as the length being 128 The am...

Page 296: ... the pointers may be the same for an empty and a full FIFO there are internal states distinguishing between these situations This means that while any value can be written to the pointer registers certain rules must be observed for the FIFO to function reliably after the pointer write Any writes to a pointer must be considered to move that pointer up Hence writing N to a pointer already holding N ...

Page 297: ... A LLE RFRXFWR MCU N A RFRXFRD Both LLE RFRXFWP Both MCU RFRXFRP Both LLE RFRXFSWP Both MCU RFRXFSRP Both N A RFTXFLEN Both MCU RFTXFTHRS N A MCU RFTXFWR LLE N A RFTXFRD Both MCU RFTXFWP Both LLE RFTXFRP Both MCU RFTXFSWP Both LLE RFTXFSRP 1 MCU if PRF_ADDR_ENTRYn CONF RETRY is 1 25 3 2 DMA It is possible to use direct memory access DMA to move data between memory and the radio See Chapter 8 for a...

Page 298: ...ng is used bit 0 is the LSB and bit 7 is the MSB Multi byte fields are little endian The detailed breakdown of the address entries ADDR_ENTRY0 ADDR_ENTRY7 is shown in Table 25 4 or Table 25 6 depending on the operational mode The Prot columns of Table 25 4 Table 25 5 and Table 25 6 list the type of protection for each entry Sem0 Entries protected by SEMAPHORE0 Should only be written by the MCU whi...

Page 299: ...earch or wait 10 Stop transmit receive immediately on Timer 2 event 2 0x6001 Sem0 PRF_TASK_CONF 11 End task on Timer 2 event 2 in first sync search or clear channel assessment No stop after first sync search or clear channel assessment Bit 6 TX_ON_CC_CONF 0 Listen until RSSI drops below given level then start Tx 1 End task if RSSI is above given level Bit 7 REPEAT_CONF For TX_ON_CC with REPEAT 1 0...

Page 300: ... 01 Include address byte in Tx FIFO no config byte 10 Include config byte and use address index in that byte to find address from PRF_ADDR_ENTRYn 11 Read address from Tx FIFO followed by config byte where address information is ignored Not allowed for PRF_TASK_CONF MODE 00 or 01 Packet configuration Bit 0 ADDR_LEN Number of address bytes 0 or 1 Bit 1 AGC_EN 0 Do not use AGC 1 Use AGC Section 25 9 ...

Page 301: ...017 Sem1 PRF_TX_RX_TIME auto retransmission given in 31 25 ns units Address structure for address number 0 See 0x6018 0x6023 PRF_ADDR_ENTRY0 Table 25 5 and Table 25 6 for details Address structure for address number 1 See 0x6024 0x602F PRF_ADDR_ENTRY1 Table 25 5 and Table 25 6 for details Address structure for address number 2 See 0x6030 0x603B PRF_ADDR_ENTRY2 Table 25 5 and Table 25 6 for details...

Page 302: ...ync word Bit 1 ENA1 Enable for secondary sync word Rx task only 0 Disable address entry for secondary sync word 1 Enable address entry for secondary sync word Bit 2 REUSE Allow reuse of transmitted packet 0 LLE deallocates packet after it has been acknowledged 1 LLE does not deallocate packet after it has been acknowledged this is up to the MCU Bit 3 AA Enable auto acknowledgement auto retranmsmis...

Page 303: ...NGTH1 the value is set to 0 by the LLE The MCU only writes to the register when it is zero the LLE only writes it to zero when it is non zero CRC value last two bytes if more than 2 CRC bytes of last 0x06 0x07 Sem1 R CRCVAL successfully received packet Number of packets transmitted For auto retransmission only acknowledged packets with new sequence number are counted For 0x08 Sem1 R N_TXDONE auto ...

Page 304: ...LLE is reset when the device enters PM2 or PM3 This means that the PRFX registers must be re initialized after coming up from one of these power modes The parts of RAM page 5 that are not listed in Table 25 7 are reserved for use by the LLE and should not be written by the MCU 25 4 Bit Stream Processor The bit stream processor BSP supports automatic insertion of CRC and detection of CRC error with...

Page 305: ...e the polynomial x9 x4 1 The whitening sequence is produced one byte at a time and the byte is bit reversed before being XORed with a received or transmitted byte Before starting reception or transmission of a packet the s and b registers must be initialized to all ones by writing a 1 to register BSP_W W_PN9_RESET As for the PN7 whitener this is done by the LLE for normal receive and transmit task...

Page 306: ... to the start of CRC calculation the d and p registers should be initialized by writing d to registers BSP_D 0 3 and p to registers BSP_P 0 3 The BSP_P 0 3 registers only must be set once whereas the BSP_D 0 3 registers should be set again for each packet In normal transmit and receive modes this is handled by the LLE which writes the value of PRF_CRC_INIT 0 3 to BSP_D 0 3 At the end of CRC calcul...

Page 307: ...icates the initialization value to use each X does not have to be the same Some examples are shown in Table 25 9 Table 25 8 Register Settings for Different CRCs Order Polynomial PRF_CRC_LEN BSP_Px PRF_CRC_INIT BSP_P0 0000 0000 PRF_CRC_INIT 0 0 BSP_P1 0000 0000 PRF_CRC_INIT 1 0 8 1 x8 a7x7 a1 x1 1 BSP_P2 0000 0000 PRF_CRC_INIT 2 0 BSP_P3 a7 a6 a5 a4 a3 a2 a11 PRF_CRC_INIT 3 X BSP_P0 0000 0000 PRF_C...

Page 308: ...ing Coprocessor mode is selected by setting BSP_MODE CP_MODE to 01 or 11 In these modes one byte to be processed is written to the BSP_DATA register and the result of processing this byte can later be read back from the same register When BSP_MODE CP_MODE is 01 the coprocessor is in receive mode where the whitener is applied before the CRC When BSP_MODE CP_MODE is 11 the coprocessor is in transmit...

Page 309: ... and the LLE programs the frequency it uses an IF on Tx as specified in PRF_RADIO_CONF TXIF This IF may be zero or 1 MHz 2 MHz or 3 MHz The recommended setting is 1 MHz A negative IF is used when PRF_CHAN FREQ 62 and a positive IF is used when PRF_CHAN FREQ 62 For all data rates the setting of MDMCTRL1 PHASE_INVERT is taken into account by the LLE when finding the setting for MDMTEST1 TX_TONE The ...

Page 310: ...a longer time means that the result may be wrong for short packets An average of n windows of length t RSSIshould only be used for packets lasting longer than n 1 tRSSI including preamble sync word and CRC The receiver must run dc offset estimation and removal The dc offset estimation mode can be controlled with MDMTEST0 DC_BLOCK_MODE For data rates of 1 Mbps and lower where the receiver runs on a...

Page 311: ...fixed as described in Section 25 9 2 The optional address is 1 byte if present the length is configured with the PRF_PKT_CONF ADDR_LEN register In the transmitter the address can be used for identification or to direct the message to a particular receiver and in the receiver the address can be used to filter out messages from unknown or unwanted transmitters and to distinguish between messages fro...

Page 312: ...O_CONF cannot be used in this case and auto commit and auto deallocate must be enabled for the Rx FIFO in RFFCFG The address byte is placed after the length byte and is present if configured in PRF_FIFO_CONF RX_ADDR_CONF The address is written in the FIFO as it was received on the air The config byte following the length byte and address byte is present if configured in PRF_FIFO_CONF RX_ADDR_CONF ...

Page 313: ...usly If an address byte is included the address index is used to determine which address entry to read the configuration from but the ADDRESS field in that address entry is ignored In auto mode the NO_ACK bit LSB of the transmitted header is set to bit 5 of the config byte If PRF_ADDR_ENTRYn CONF FIXEDSEQ where n is the index of the address used is 1 the SEQ field of the transmitted header is take...

Page 314: ... transmitted The length is given by PRF_ADDR_ENTRYn ACKLENGTHk and the address and sequence number are as described in Section 25 9 2 3 2 In order to flush the buffers for address n issue the command CMD_FLUSH_ACK n see Table 25 12 This causes the LLE to write PRF_ADDR_ENTRYn ACKLENGTH0 and PRF_ADDR_ENTRYn ACKLENGTH1 to 0 and clear PRF_ADDR_ENTRYn SEQSTAT ACK_PAYLOAD_SENT If no task is running the...

Page 315: ...rs for address 0 0x31 CMD_FLUSH_ACK1 Flush the ACK payload buffers for address 1 0x32 CMD_FLUSH_ACK2 Flush the ACK payload buffers for address 2 0x33 CMD_FLUSH_ACK3 Flush the ACK payload buffers for address 3 0x34 CMD_FLUSH_ACK4 Flush the ACK payload buffers for address 4 0x35 CMD_FLUSH_ACK5 Flush the ACK payload buffers for address 5 0x36 CMD_FLUSH_ACK6 Flush the ACK payload buffers for address 6...

Page 316: ...g time to allow the LNA to stabilize starts sync search The time to start Rx with this mode is the same as for ordinary start of Rx If PRF_RADIO_CONF DCWB is 1 the LLE writes the dc offset estimate read out at the end of the packet into the dc offset override register provided that the received packet did not have a CRC error This is suited for the delayed dc offset mode where the override value f...

Page 317: ...peration The possible values of PRF_ENDCAUSE are listed in Table 25 14 If PRF_CHAN SYNTH_ON is 1 the synthesizer is not turned off after the task ends This can be used to start a new task immediately on the same channel and get faster start of Rx or Tx To do so the next task should be started with PRF_CHAN FREQ set to 127 Note that the synthesizer should not be allowed to run for a long time after...

Page 318: ...the packet That signal can be extra preamble bytes or tone The length required for this signal depends on the RSSI accuracy setting in MDMTEST0 RSSI_ACC see Section 25 7 An average of n windows of length t RSSI requires the extra signal to last at least n 1 tRSSI Extra preamble bytes can be set up using MDMCTRL2 NUM_PREAM_BYTES Note that the extra signal required comes in addition to the 1 preambl...

Page 319: ...er applies but the Timer 2 event 2 timeout does not apply after sync is obtained or while waiting for Timer 2 event 1 to restart listening If sync is obtained the LLE starts reading the packet If sync is found on a packet the time of sync is captured by the Timer 2 capture function see Section 22 1 10 25 9 2 3 1 Basic Mode This section describes the receive operation if PRF_TASK_CONF MODE is 00 or...

Page 320: ...ify the entry or entries and restart the receiver 25 9 2 3 2 Auto Mode This section describes the receive operation if PRF_TASK_CONF MODE is 10 or 11 If PRF_PKT_CONF ADDR_LEN is 1 the address byte is compared against PRF_ADDR_ENTRYn ADDRESS where n ranges from 0 to 7 It is compared against PRF_ADDR_ENTRYn ADDRESS for the values of n where the entry is enabled for the received sync word If there is...

Page 321: ...load length and whether the received packet is a retransmission to be ignored the interrupts are generated as shown in Table 25 17 The table also shows which of the counters among the RAM registers are to be updated Table 25 17 Interrupt and Counter Operation for Received Messages CRC Result Ignore Length Counter Incremented Interrupt Raised OK No 0 RXOK PRF_ADDR_ENTRYn N_RXOK OK No 0 RXEMPTY PRF_...

Page 322: ...the receiver or transmitter was running an RXTXABO interrupt is also raised If CMD_STOP is received while in sync search the task ends immediately with TASK_RXTIMEOUT as the end cause If CMD_STOP is received while receiving or while transmitting an ACK or in the transition between those the task ends with TASK_STOP as the end cause after the packet is fully received and if ACK is to be sent the AC...

Page 323: ...ter the length byte is read so if the FIFO contains fewer bytes than indicated in the length field a Tx FIFO underflow interrupt is raised by the FIFO hardware 25 9 2 4 1 Basic Mode This section describes the transmit operation if PRF_TASK_CONF MODE is 00 or 01 If PRF_TASK_CONF MODE is 01 the length field is calculated from the length field in the FIFO and transmitted It is up to the MCU to ensure...

Page 324: ... to listen for an acknowledgment To listen for acknowledgment the receiver is configured at a time given by the PRF_TX_RX_TIME register Synthesizer recalibration is performed only if there is time The unit looks for sync The sync search times out at the time given by PRF_SEARCH_TIME If sync is found the packet is received into the Rx FIFO If PRF_PKT_CONF ADDR_LEN is 1 the address byte is compared ...

Page 325: ...s not incremented This means that by default the packet retransmission is attempted in the next task If this is not desired the packet must be removed from the FIFO This can be done either by issuing a CMD_TXFIFO_RESET this also removes any subsequent packets in the Tx FIFO by reading out the packet using the RFTXFRD register and issuing a CMD_TX_FIFO_DEALLOC command or by Tx FIFO pointer manipula...

Page 326: ...ASKERR_TXFIFO is supposed to start or Tx FIFO is in an invalid state also raised Rx FIFO went overfull while receiving an ACK that TASKERR_RXFIFO RXFIFOFULL interrupt is also raised was not otherwise to be discarded Received command for starting new task or If transmitter was running an RXTXABO CMD_SHUTDOWN or observed Timer 2 event 2 with TASK_ABORT interrupt is also raised PRF_TASK_CONF STOP_CON...

Page 327: ...D_SEND_EVENT2 is observed during the task the behavior depends on PRF_TASK_CONF STOP_CONF 00 Nothing happens 01 If received while transmitting a packet or waiting for or receiving an ACK or in the transition between those the task ends with TASK_STOP as the end cause after the packet is fully transmitted and if ACK is expected the ACK is received or given up If received while waiting for Timer 2 e...

Page 328: ...is register to 0 disables the time out In case of a time out the task ends for a normal sync search or a packet is retransmitted in case of an ACK sync search NOTE The time given by PRF_SEARCH_TIME is denoted tSearch and the time given by PRF_RX_TX is denoted tRx Tx The setup and wait time for the synthesizer receiver and transmitter are denoted tSynth tTx and tRx respectively Figure 25 12 Timing ...

Page 329: ...w ti com Link Layer Engine NOTE The time given by PRF_TX_DELAY is denoted t Tx_Delay the time given by PRF_SEARCH_TIME is denoted tSearch the time given by PRF_RETRANS_DELAY is denoted tRetrans and the time given by PRF_TX_RX is denoted tTx Rx The setup and wait times for the synthesizer receiver and transmitter are denoted tSynth tTx and tRx respectively Figure 25 13 Timing of Packets in Tx Tasks...

Page 330: ...his register Reading the RFPSRND register is equivalent to reading RNDL then writing 01 to ADCCON1 RCTL For seeding the pseudo random number generator and for tasks where higher entropy of the random numbers is needed the radio can be used as a true random generator The register RFRND provides access to the least significant bits of the radio ADC which is random when noise is received In order to ...

Page 331: ...eration Table 25 22 Packet Sniffer Modes of Operation MDMCTRL3 RFC_SNIFF_CTRL Description 00 Packet sniffer disabled Data output from BSP Tx data including CRC is whitened if the whitener is 01 enabled Rx data including CRC is always de whitened Data output from modulator Only Tx data before whitening is output Any CRC 10 bytes are 0 11 Data output from the demodulator Only Rx data before de white...

Page 332: ... RF interrupt flags 2 RFIRQF1 0x91 RF interrupt flags 3 RFERRF 0xBF RF error interrupt flags 4 RFD 0xD9 RF data 5 RFST 0x6189 LLE and FIFO commands 25 12 1 2 XREG Registers Table 25 23 XREG Register Overview Address Hex 0x0000 0x001 0x002 0x003 0x6180 FRMCTRL0 RFIRQM0 RFIRQM1 RFERRM 0x6184 FREQCTRL FREQTUNE TXPOWER TXCTRL 0x6188 LLESTAT SEMAPHORE0 SEMAPHORE1 0x618C SEMAPHORE2 RFSTAT RSSI RFPSRND 0...

Page 333: ...L1 sync word Use inverse of preamble for frequency 6192 C0 C0 MDMCTRL2 offset estimation assuming MSB first Set RSSI mode to peak detect after 6193 63 63 MDMCTRL3 sync 619A 33 3F Receiver currents RXCTRL 619B 55 5A Prescaler and mixer currents FSCTRL 61A0 3A 7F LNA gain LNAGAIN Sets Tx anti aliasing filter to appropriate 61BC 03 03 TXFILTCFG bandwidth 6186 E1 E1 Tx power 0 dBm TXPOWER 6187 19 19 D...

Page 334: ...rmat and the correlation threshold in MDMCTRL1 should be adjusted according to the sync word length see Section 25 7 In addition to these modifications registers must be set in order to set up the modulation format packet handling etc as explained throughout this chapter 25 12 3 SFR Register Descriptions RFIRQF0 0xE9 RF Interrupt Flags Bit Name Reset R W Description No 7 4 0000 R0 Reserved 3 RXTHS...

Page 335: ...upt pending RFERRF 0xBF RF Error Interrupt Flags Bit Name Reset R W Description No 7 0 R W0 Reserved 6 RXFIFOFULL 0 R W0 Rx FIFO is full when trying to store received data 0 No interrupt pending 1 Interrupt pending 5 LLEERR 0 R W0 LLE command or parameter error 0 No interrupt pending 1 Interrupt pending 4 RXTXABO 0 R W0 Receive or transmit operation aborted 0 No interrupt pending 1 Interrupt pendi...

Page 336: ... calculation 1 The sync word is included in the crc calculation Only to be used with whitening disabled 0 ENDIANNESS 0 R W 0 The data goes LSB first over the air 1 The data goes MSB first over the air RFIRQM0 0x6181 RF Interrupt Masks Bit Name Reset R W Description No 7 4 0000 R0 Reserved 3 RXTHSHUP 0 R W Rx FIFO goes above its upper threshold 0 Interrupt disabled 1 Interrupt enabled 2 TXTHSHUP 0 ...

Page 337: ...ed 1 Interrupt enabled 0 RXOK 0 R W Packet received correctly 0 Interrupt disabled 1 Interrupt enabled RFERRM 0x6183 RF Error Interrupt Masks Bit Name Reset R W Description No 7 0 R W Reserved 6 RXFIFOFULL 0 R W RX FIFO is full when trying to store received data 0 Interrupt disabled 1 Interrupt enabled 5 LLEERR 0 R W LLE command or parameter error 0 Interrupt disabled 1 Interrupt enabled 4 RXTXABO...

Page 338: ...tings Bit Name Reset R W Description No 7 0 R0 Reserved 6 1 R W Reserved 5 4 DAC_CURR 1 0 10 R W Change the current in the DAC to change the current steps 3 2 DAC_DC 1 0 10 R W Adjusts the dc level to the Tx mixer 1 0 TXMIX_CURRENT 1 0 01 R W Transmit mixers core current Current increases with increasing setting LLESTAT 0x6188 LLE Status Bit Name Reset R W Description No 7 5 000 R0 Reserved 4 AGC_...

Page 339: ...ng 11 Error 4 SFD 0 R High when the sync word has been sent in TX or when sync has been obtained in RX 3 CAL_RUNNING 0 R Frequency synthesizer calibration status 0 Calibration done or not started 1 Calibration in progress 2 LOCK_STATUS 0 R 1 when PLL is in lock 0 otherwise 1 TX_ACTIVE 0 R Status signal active when the LLE is in one of the transmit states 0 RX_ACTIVE 0 R Status signal active when t...

Page 340: ...ary 1 represented with positive frequency deviation 1 Inverted phase binary 0 represented with positive frequency deviation binary 1 represented with negative frequency deviation MDMCTRL1 0x6191 Modem Configuration Bit Name Reset R W Description No 7 6 FOC_MODE 01 R W Frequency offset average filter behavior 00 No frequency offset compensation done 01 Freeze frequency offset estimate after sync 10...

Page 341: ... bytes 0011 4 leading preamble bytes 1111 16 leading preamble bytes MDMCTRL3 0x6193 Modem Configuration Bit Name Reset R W Description No 7 6 SYNC_MODE 1 0 01 R W 00 Correlation above threshold is sufficient as sync criterion 01 Correlation value above threshold and data decision on all symbols of sync word is used as sync criterion 10 Correlation value above threshold and data decision on all sym...

Page 342: ... 0x00 R W Contains bits 15 8 of the primary synchronization word SW2 0x6197 Primary Sync Word Byte 2 Bit Name Reset R W Description No 7 0 SYNC_WORD 23 16 0x00 R W Contains bits 23 16 of the primary synchronization word SW3 0x6198 Primary Sync Word Byte 3 Bit Name Reset R W Description No 7 0 SYNC_WORD 31 24 0x00 R W Contains bits 31 24 of the primary synchronization word SW4 0x61F8 Secondary Sync...

Page 343: ...y Synthesizer Tuning Bit Name Reset R W Description No 7 6 PRE_CURRENT 1 0 01 R W Prescaler current setting 5 4 LODIV_BUF_CURRENT_TX 01 R W Adjusts current in mixer and PA buffers lodiv_buf_current Used when 1 0 lle_tx_active 1 3 2 LODIV_BUF_CURRENT_RX 01 R W Adjusts current in mixer and PA buffers lodiv_buf_current Used when 1 0 lle_tx_active 0 1 0 LODIV_CURRENT 1 0 01 R W Adjusts divider current...

Page 344: ...ow 101 Mean of two 21 3 µs average windows 110 Reserved 111 Mean of four 21 3 µs average windows 4 0 R W Reserved always write 0 3 2 DC_BLOCK_LENGTH 1 0 00 R W Controls the number of samples to be accumulated between each dump of the accumulate and dump filter used in dc removal 00 16 samples 01 32 samples 10 64 samples 11 128 samples 1 0 DC_BLOCK_MODE 1 0 01 R W Selects the mode of operation 00 M...

Page 345: ...PHASE_INVERT is 1 the sign of the frequency is inverted 0 8 MHz 1 6 MHz 2 4 MHz 3 3 MHz 4 2 MHz 5 1 MHz 6 500 kHz 7 250 kHz 8 125 kHz 9 4 kHz 10 0 Hz 11 4 kHz 12 125 kHz 13 250 kHz 14 500 kHz 15 1 MHz 16 2 MHz 17 3 MHz 18 4 MHz 19 6 MHz 20 8 MHz ATEST 0x61A9 Analog Test Control Bit Name Reset R W Description No 7 6 00 R0 Reserved Read as zero 5 0 ATEST_CTRL 5 0 00 0000 R W Controls the analog test...

Page 346: ...ent 1 to start a task Low Not waiting for Timer 2 event 1 High Command processed event 1 not yet received 00 1111 agc_lowgain High if the AGC algorithm has reduced the front end gain low otherwise 01 0011 fsc_lock High when PLL is in lock low otherwise 01 1011 pa_pd Power amplifier power down signal 10 1100 lnamix_pd Low noise amplifier power down signal 11 0000 dem_sync_found High when demodulato...

Page 347: ... 4 0000 R0 Reserved 3 2 11 R W Reserved 1 0 FC 11 R W Sets TX anti aliasing filter to appropriate bandwidth Reduces spurious emissions close to signal For the best value to use see Table 25 24 and Table 25 25 RFRND 0x61BF Random Data Bit Name Reset R W Description No 7 0 RND 0x00 R Random bits provided analog part is in random number generation mode receiver running without sync RFRAMCFG 0x61C0 Ra...

Page 348: ...ed never 0x10 Never 0x11 A byte is read from Tx FIFO and more bytes remain or when a byte arrives in Tx FIFO and it was previously empty 0x12 A byte is written to Tx FIFO and there is available space left or when there becomes available space when the Tx FIFO was full 0x13 Tx FIFO is empty 0x14 Tx FIFO is full 0x15 Tx FIFO length equals RFTXFTHRS after a write to Tx FIFO 0x16 Tx FIFO is read when ...

Page 349: ...ription No 7 6 0 R Reserved 5 TXAUTOCOMMIT 1 R W 0 Commit Tx FIFO only on command 0x95 1 Always set RFTXSWP RFTXWP 4 TXFAUTODEALLOC 0 R W 0 Deallocate Tx FIFO only on command 0x92 1 Always set RFTXFSRP RFTXFRP 3 2 0 R Reserved 1 RXAUTOCOMMIT 0 R W 0 Commit Rx FIFO only on command 0x85 1 Always set RFRXSWP RFRXWP 0 RXFAUTODEALLOC 1 R W 0 Deallocate Rx FIFO only on command 0x82 1 Always set RFRXFSRP...

Page 350: ...art of written package This is the point to which the write 0000 pointer can be reset if a discard command is issued RFRXFSRP 0x61CF Rx FIFO Start of Frame Read Pointer Bit Name Reset R W Description No 7 0 R Reserved 6 0 D 000 R W Rx FIFO start of read package This is the start of the allocated part of the 0000 Rx FIFO RFTXFLEN 0x61D0 Tx FIFO Length Bit Name Reset R W Description No 7 0 D 0x00 R ...

Page 351: ...6 0 D 000 R W Tx FIFO start of written package This is the point to which the write 0000 pointer can be reset if a discard command is issued RFTXFSRP 0x61D7 Tx FIFO Start of Frame Read Pointer Bit Name Reset R W Description No 7 0 R Reserved 6 0 D 0x00 R W Tx FIFO start of read package This is the start of the allocated part of the Tx FIFO BSP_P0 0x61E0 CRC Polynomial Byte 0 Bit Name Reset R W Des...

Page 352: ...s back w register BSP_W 0 is set to w6 BSP_W 1 is set to w5 and so on up to BSP_W 6 is set to w0 BSP_MODE 0x61E9 Bit Stream Processor Configuration Bit Name Reset R W Description No 7 0 R0 Reserved Read as zero 6 CP_BUSY 0 R Coprocessor mode busy Goes to 1 after a byte has been written to BSP_DATA Goes to 0 when a byte is ready to be read back from BSP_DATA 5 CP_READOUT 0 R W Coprocessor mode read...

Page 353: ...channel When manual dc override is selected the override value is written to this register DC_Q_H 0x61FF Quadrature Phase DC Offset Estimate High Byte Bit Name Reset R W Description No 7 0 DC_Q 15 8 0x00 R W When running dc estimation this register reflects the 8 MSBs of the dc estimate in the Q channel When manual dc override is selected the override value is written to this register IVCTRL 0x626...

Page 355: ...CC2530 reference design The voltage regulator is disabled in power modes PM2 and PM3 see Chapter 4 When the voltage regulator is disabled register and RAM contents are retained while the unregulated 2 V to 3 6 V power supply is present NOTE The voltage regulator should not be used to provide power to external circuits 355 SWRU191C April 2009 Revised January 2012 Voltage Regulator Submit Documentat...

Page 357: ...ferent software offerings in the sections below For example a user designing a ZigBee device should use the CC2530F256 as the Z Stack requires in most cases more than 128 KB of flash and needs the 8 KB RAM Topic Page 27 1 SmartRF Software for Evaluation www ti com smartrfstudio 358 27 2 RemoTI Network Protocol www ti com remoti 358 27 3 SimpliciTI Network Protocol www ti com simpliciti 359 27 4 TI...

Page 358: ...re advanced features based on bidirectional RF communication ZigBee Radio Frequency for Consumer Electronics RF4CE is the result of a recent agreement between the ZigBee Alliance and the RF4CE Consortium http www zigbee org rf4ce and has been designed to be deployed in a wide range of remotely controlled audio visual consumer electronics products such as TVs and set top boxes ZigBee RF4CE promises...

Page 359: ...duty cycle Ease of use For more information about the SimpliciTI network protocol see the Texas Instruments SimpliciTI network protocol Web site www ti com simpliciti 27 4 TIMAC Software www ti com timac TIMAC software is an IEEE 802 15 4 medium access control software stack for TI s IEEE 802 15 4 transceivers and System on Chips You can use TIMAC when you Need a wireless point to point or point t...

Page 360: ...nsitivity The Z Stack software has been awarded the ZigBee Alliance s golden unit status for both the ZigBee and ZigBee PRO stack profiles and is used by ZigBee developers worldwide Z Stack software is well suited for Smart energy AMI Home automation Commercial building automation Medical assisted living or personal health and hospital care Monitoring and control applications Wireless sensor netwo...

Page 361: ...al Regulations CMRR Common mode rejection ratio CPU Central processing unit CRC Cyclic redundancy check CSMA CA Carrier sense multiple access with collision avoidance CSP CSMA CA strobe processor CTR Counter mode encryption CW Continuous wave DAC Digital to analog converter DC Direct current DMA Direct memory access DSM Delta sigma modulator DSSS Direct sequence spread spectrum ECB Electronic code...

Page 362: ... significant bit byte MAC Medium access control MAC Message authentication code MCU Microcontroller unit MFR MAC footer MHR MAC header MIC Message integrity code MISO Master in slave out MOSI Master out slave in MPDU MAC protocol data unit MSB Most significant bit byte MSDU MAC service data unit MUX Multiplexer NA Not applicable available NC Not connected OFB Output feedback encryption O QPSK Offs...

Page 363: ...SINAD Signal to noise and distortion ratio SPI Serial peripheral interface SRAM Static random access memory ST Sleep timer T R Tape and reel T R Transmit receive THD Total harmonic distortion TI Texas Instruments TX Transmit UART Universal asynchronous receiver transmitter USART Universal synchronous asynchronous receiver transmitter VCO Voltage controlled oscillator VGA Variable gain amplifier WD...

Page 365: ...omer support third party and university programs The Low Power RF E2E Online Community provides you with technical support forums videos and blogs and the chance to interact with fellow engineers from all over the world With a broad selection of product solutions end application possibilities and the range of technical support Texas Instruments offers the broadest low power RF portfolio We make RF...

Page 366: ...s and independent design houses that provide a series of hardware module products and design services including RF circuit low power RF and ZigBee design services Low power RF and ZigBee module solutions and development tools RF certification services and RF circuit manufacturing Need help with modules engineering services or development tools Search the Low Power RF Developer Network to find a su...

Page 367: ...006 pdf 2 CC2530 Data Sheet SWRS081 3 CC2531 Data Sheet SWRS086 4 CC2533 Data Sheet SWRS087 5 CC2540 Data Sheet SWRS084 6 CC2541 Data Sheet SWRS110 7 Bluetooth Core Technical Specification document version 4 0 https www bluetooth org technical specifications adopted htm 8 Universal Serial Bus Revision 2 0 specification http www usb org developers docs usb_20_101111 zip 367 SWRU191C April 2009 Revi...

Page 369: ...0 CC2531 CC2540 in several places 75 83 86 Changed R W0 to R W for T3CTL bit 3 128 Changed R W0 to R W for T4CTL bit 3 131 Updated description for Watchdog Timer Control 161 Included relevant parts of CC2541 Timer 2 Radio Timer chapter in this chapter and then deleted that one 207 Added CC2541 information to MAC timer description 207 Inserted Long Compare section for CC2541 209 Added two new inter...

Page 370: ...for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agre...

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