Texas Instruments BQ25157, Manual

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When configuring the ADC comparators, it is recommended to first disable the comparator through the
ADCCTRLx registers and allow the ADC to complete a measurement on the desired channel before enabling or
reconfiguring the comparator by setting the ADC_COMPx_2:0 bits to the desired channel. This would prevent
the comparator from sending an interrupt based on an outdated ADC reading when the comparator is enabled or
reconfigured, especially in battery only operation where the ADC is not continuously performing measurements
in all the channels.
9.3.4 VDD LDO
The device integrates a low current always-on LDO that serves as the digital I/O supply to the device. This LDO
is supplied by VIN or by BAT. The end user may be able to draw up to 10 mA of current through the VDD pin to
power a status LED or provide an IO supply. The VDD LDO will remain on through all power states with the
exception of Ship Mode.
9.3.5 Load Switch/LDO Output and Control
The device integrates a low Iq load switch which can also be used as a regulated output. The LDO/LS has a
dedicated input pin VINLS and can support up to 150 mA of load current.
The LS/LDO may be enabled/disabled through I
2
C. The output voltage is programmable using the LS_LDO bits
in the registers. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to
VINLS pin.
The output voltage is programmable using the LS_LDO bits in the registers.The LS/LDO voltage is calculated
using the following equation: V
LSLDO
= 0.6 V + LS_LDOCODE × 100 mV up to 3.7 V. All higher codes will set the
output to 3.7 V.
Table 9-3. LDO Mode Control
I2C EN_LS_LDO LS_CONFIG LS/LDO OUTPUT
0 0 Pulldown
0 1 Pulldown
1 0 LDO
1 1 Load Switch
The current capability of the LDO will depend on the VINLS input voltage and the programmed output voltage.
When the LS/LDO output is disabled through the register, an internal pull-down will discharge the output.
The LDO has output current limit protection, limiting the output current in the event of a short in the output. When
the LDO output current limit trips and is active for at least 1 ms, the device will set a flag and send an interrupt to
the host. The LDO may be set to operate as a load switch by setting the LS_SWITCH_CONFG bit. Note that in
order to change the configuration the LDO must be disabled first, then the LS_SWITCH_CONFG bit is set for it
to take effect.This is not the case when updating the LDO output voltage which can be done on the fly without
the need of disabling the LDO first.
9.3.6 PMID Power Control
The BQ25157 offers the option to control PMID through the I
2
C PMID_MODE bits. These bits can force PMID to
be supplied by BAT instead of IN, even if V
IN
> V
BAT
+ V
SLP
. They can also disconnect PMID, pulling it down or
leaving it floating. Table 9-4 shows the expected device behavior based on the PMID_MODE setting as detailed
in Table 9-4 below.
Table 9-4. PMID_MODE Control
PMID_MODE DESCRIPTION PMID SUPPLY PMID PULL-DOWN
00 Normal Operation IN or BAT Off
01 Force BAT Power BAT Off
10 PMID Off - Floating None Off
11 PMID Off - Pulled Down None On
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BQ25157
SLUSEC5 – DECEMBER 2020
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