DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 9-10. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see
). This releases the bus and stops the communication
link with the addressed slave. All I
2
C compatible devices must recognize the stop condition. Upon the receipt of
a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the
slave I
2
C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section will result in FFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
Not Acknowledge
Acknowledge
Clock Pulse for
Acknowledgement
1
2
8
9
START
Condition
Figure 9-11. Acknowledge on the I
2
C Bus
SLUSEC5 – DECEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
33
Product Folder Links:
Summary of Contents for BQ25157
Page 107: ...D Max E Max 2 045 mm Min 1 645 mm Min 1 985 mm 1 585 mm...
Page 108: ......
Page 109: ......
