Texas Instruments BQ25157, Manual

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9.5.1.9 MASK1 Register (Address = 0x8) [reset = 0x0]
MASK1 is shown in Figure 9-24 and described in Table 9-18 .
Return to Summary Table .
Figure 9-24. MASK1 Register
7 6 5 4 3 2 1 0
VIN_OVP_FAU
LT_MASK
RESERVED BAT_OCP_FAU
LT_MASK
BAT_UVLO_FA
ULT_MASK
TS_COLD_MA
SK
TS_COOL_MA
SK
TS_WARM_MA
SK
TS_HOT_MAS
K
R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0
Table 9-18. MASK1 Register Field Descriptions
Bit Field Type Reset Description
7 VIN_OVP_FAULT_MASK R/W 1b0 Mask for VIN_OVP_FAULT interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
6 RESERVED R/W 1b0 Reserved
5 BAT_OCP_FAULT_MASK R/W 1b0 Mask for BAT_OCP_FAULT interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
4 BAT_UVLO_FAULT_MAS
K R/W 1b0 Mask for BAT_UVLO_FAULT interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
3 TS_COLD_MASK R/W 1b0 Mask for TS_COLD interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
2 TS_COOL_MASK R/W 1b0 Mask for TS_COOL interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
1 TS_WARM_MASK R/W 1b0 Mask for TS_WARM interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
0 TS_HOT_MASK R/W 1b0 Mask for TS_HOT interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
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BQ25157
SLUSEC5 – DECEMBER 2020
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