Texas Instruments BQ25157, Manual

Page: 51 / 110

9.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]
MASK3 is shown in Figure 9-26 and described in Table 9-20 .
Return to Summary Table .
Figure 9-26. MASK3 Register
7 6 5 4 3 2 1 0
RESERVED WD_FAULT_M
ASK
SAFETY_TMR_
FAULT_MASK
LDO_OCP_FA
ULT_MASK
RESERVED MRWAKE1_TI
MEOUT_MASK
MRWAKE2_TI
MEOUT_MASK
MRRESET_WA
RN_MASK
R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0
Table 9-20. MASK3 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 1b0 Reserved
6 WD_FAULT_MASK R/W 1b0 Mask for WD_FAULT Interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
5 SAFETY_TMR_FAULT_M
ASK R/W 1b0 Mask for SAFETY_TIMER_FAULT Interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
4 LDO_OCP_FAULT_MASK R/W 1b0 Mask for LDO_OCP_FAULT Interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
3 RESERVED R/W 1b0 Reserved
2 MRWAKE1_TIMEOUT_M
ASK R/W 1b0 Mask for MRWAKE1_TIMEOUT Interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
1 MRWAKE2_TIMEOUT_M
ASK R/W 1b0 Mask for MRWAKE2_TIMEOUT Interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
0 MRRESET_WARN_MASK R/W 1b0 Mask for MRRESET_WARN Interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
www.ti.com
BQ25157
SLUSEC5 – DECEMBER 2020
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 51
Product Folder Links: BQ25157