Texas Instruments BQ25157, Manual

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9.5.1.8 MASK0 Register (Address = 0x7) [reset = 0x0]
MASK0 is shown in Figure 9-23 and described in Table 9-17 .
Return to Summary Table .
Figure 9-23. MASK0 Register
7 6 5 4 3 2 1 0
RESERVED CHRG_CV_MA
SK
CHARGE_DON
E_MASK
IINLIM_ACTIVE
_MASK
VDPPM_ACTIV
E_MASK
VINDPM_ACTI
VE_MASK
THERMREG_A
CTIVE_MASK
VIN_PGOOD_
MASK
R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0 R/W-1b0
Table 9-17. MASK0 Register Field Descriptions
Bit Field Type Reset Description
7 RESERVED R/W 1b0 Reserved
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
6 CHRG_CV_MASK R/W 1b0 Mask for CHRG_CV interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
5 CHARGE_DONE_MASK R/W 1b0 Mask for CHARGE_DONE interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
4 IINLIM_ACTIVE_MASK R/W 1b0 Mask for IINLIM_ACTIVE interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
3 VDPPM_ACTIVE_MASK R/W 1b0 Mask for VDPPM_ACTIVE interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
2 VINDPM_ACTIVE_MASK R/W 1b0 Mask for VINDPM_ACTIVE interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
1 THERMREG_ACTIVE_M
ASK R/W 1b0 Mask for THERMREG_ACTIVE interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
0 VIN_PGOOD_MASK R/W 1b0 Mask for VIN_PGOOD interrupt
1b0 = Interrupt Not Masked
1b1 = Interrupt Masked
BQ25157
SLUSEC5 – DECEMBER 2020
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