7 Pin Configuration and Functions
IN
PMID
BAT
GND
/PG
PMID
BAT
TS
/MR
/CE
NC
ADCIN
VDD
/INT
/LP
LSLDO
VIO
SDA
SCL
VINLS
A
B
C
D
E
1
2
3
4
Figure 7-1. YFP Package 20-Pin DSBGA Top View
Table 7-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
IN
A1
I
DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with
at least 1-µF of capacitance using a ceramic capacitor.
PMID
A2, B2
I/O
Regulated System Output. Connect 10-µF capacitor from PMID to GND as close to the
PMID and GND pins as possible. (at least 3-µF of ceramic capacitance with DC bias de-
rating). Note: Shorting PMID to IN pin is not recommended as it may cause large discharge
current from battery to IN if IN pin is not truly floating.
GND
A4
PWR
Ground connection. Connect to the ground plane of the circuit.
VDD
D1
O
Digital supply LDO. Connect a 2.2-µF from this pin to ground. A 4.7-µF capacitor to ground
recommended if loaded externally.
CE
C2
I
Charge Enable. Drive CE low or leave disconnected to enable charging when VIN is valid.
Drive CE high to disable charge when VIN is present. CE is pulled low internally with 900-kΩ
resistor. CE has no effect when VIN is not present.
SCL
E3
I/O
I
2
C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA
E2
I
I
2
C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
LP
D3
I
Low Power Mode Enable. Drive this pin low to set the device in low power mode when
powered by the battery. This pin must be driven high to allow I
2
C communication when VIN
is not present. LP is pulled low internally with 900-kΩ resistor. This pin has no effect when
VIN is present.
ADCIN
C4
I
Input Channel to the ADC. Maximum ADC range 1.2 V. If not used it may be left floating or
connect to ground.
MR
C1
I
Manual Reset Input. MR is a general purpose input that must be held low for greater than
t
HWRESET
to go into HW Reset and power cycle the output rails. If MR is also used to wake
up the device out of Ship Mode when pressed for at least t
WAKE1
. MR has in internal 125-kΩ
pull-up resistor to BAT.
SLUSEC5 – DECEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
5
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