Tektronix LTA7P Series, Service Manual

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Specifications
TLA7Nx, TLA7Px, & TLA7Qx Logic Analyzer Module Service Manual
1- 3
Table 1- 2: LA module clocking (Cont.)
Characteristic Description
TLA7N4, TLA7P4, TLA7Q4 4
n
Setup and hold window size
(data and qualifiers) Maximum window size = Maximum channel-to-channel skew + (2 x sample
uncertainty) + 0.4 ns
Maximum setup time = User interface setup time + 0.8 ns
Maximum hold time = User interface hold time + 0.2 ns
Maximum setup time for slave module of merged pair =
User Interface setup time + 0.8 ns
Maximum hold time for slave module of merged pair =
User Interface hold time + 0.7 ns
Examples: for a P6417 or a P6418 probe and user interface
setup and hold of 2.0/0.0 typical:
Maximum window size = 1.6 ns + (2 x 500 ps) + 0.4ns = 3.0 ns
Maximum setup time = 2.0 ns + 0.8 ns = 2.8 ns
Maximum hold time = 0.0 ns + 0.2 ns = 0.2ns
Setup and hold window size
(data and qualifiers)
(Typical) Channel-to-channel skew (
typical
) + (2 x sample uncertainty)
Example: for P6417 or P6418 Probe = 1 ns + (2 x 500 ps) = 2 ns
Setup and hold window range The setup and hold window can be moved for each channel group from +8.5 ns (Ts) to
--7.0 ns (Ts) in 0.5 ns steps (setup time). Hold time follows the setup time by the setup
and hold window size.
n
Maximum synchronous clock rate
4
200 MHz in full speed mode (5 ns minimum between active clock edges)
100 MHz in half speed mode (10 ns minimum between active clock edges)
Demux clocking
Demux Channels
TLA7N3, TLA7N4, TLA7P4, TLA7Q4, Channels multiplex as follows:
A3(7:0) to
D3(7:0)
A2(7:0) to D2(7:0)
A1(7:0) to D1(7:0)
A0(7:0) to D0(7:0)
TLA7N1, TLA7N2, TLA7P2, TLA7Q2 Channels multiplex as follows:
A3(7:0) to
C3(7:0)
A2(7:0) to C2(7:0)
A1(7:0) to D1(7:0) TLA7N2, TLA7P2, TLA7Q2 only
A0(7:0) to D0(7:0) TLA7N2, TLA7P2, TLA7Q2 only
Time between DeMux clock edges
4
(Typical)
5 ns minimum between DeMux clock edges in full-speed mode
10 ns minimum between DeMux clock edges in half-speed mode
Time between DeMux store clock edges
4
(Typical)
10 ns minimum between DeMux master clock edges in full-speed mode
20 ns minimum between DeMux master clock edges in half-speed mode
Data Rate (Typical)
TLA7N1, TLA7N2, TLA7P2, TLA7Q2,
TLA7N3, TLA7N4, TLA7P4, TLA7Q4, 400 MHz (200 MHz option required) half channel.
(Requires channels to be multiplexed.)
These multiplexed channels double the memory depth.