Synopsys DesignWare ARC AXC003, User Manual, Page: 68 / 145

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DesignWare ARC AXC003 CPU Card User Guide Controlling the Memory Map
Synopsys, Inc. Version 6323-018
May 2017
Table 28 AXC003 CPU Card Target Slaves
Slave Number Target Slave
0 No slave selected (default slave provides response)
1 DDR controller
2 SRAM controller
3 AXI tunnel
4 AXI2APB bridge
5 Internal ROM controller
6 I/O Coherency port
7 Reserved
The AXI tunnel slave transparently forwards the received address to the corresponding AXI
tunnel master on the ARC SDP Mainboard. The address map as seen by this master is
defined by control registers of the Mainboard. For apertures selecting the AXI Tunnel, it is
best to set the address offset such that the address issued by the master on the other side
and the original address are identical. This can be achieved by setting the
SLV_OFFSET
field
of the corresponding register to the aperture number.
The memory map as seen by the AXI2APB bridge is described in Memory Map of the Local
Peripherals on page 71.
Setting Up the AXI Masters on the ARC SDP Mainboard
The address map of the AXI masters on the ARC SDP Mainboard is defined in a similar way
as described in the
“
Setting Up the AXI Masters on the AXC003 CPU Card
” section above.
Table 29 lists the target slaves that are available on the ARC SDP Mainboard. Refer to the
ARC SDP Mainboard User Guide [5] for more details.
Table 29 ARC SDP Mainboard Target Slaves
Slave Number Target Slave
0 No slave selected (default slave provides response)
1 TUNNEL0 (AXI tunnel to/from AXC003 CPU Card)
2 TUNNEL1 (AXI tunnel to/from HAPS System)
3 SRAM controller (for Mainboard RAM)
4 AXI2APB (control/status interface of peripherals)
The AXI tunnel slaves transparently forward the received address to the corresponding AXI
tunnel masters on the AXC003 CPU Card or the HAPS system. For TUNNEL0 this address
is then decoded according to the memory map programmed for the AXI tunnel master on the