139
Detailed Core Configurations
DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018
Synopsys, Inc.
May 2017
Configuration
Option
Description
HS36
HS38x2
Timer 0
+
+
timer_0_int_level
Interrupt level (and implicitly the priority: level
0 is highest)
1
1
Timer 1
+
+
timer_1_int_level
Interrupt level (and implicitly the priority: level
0 is highest)
0
0
Real-time Counter
+
-
Interrupt Controller
number_of_
interrupts
Total number of interrupts
32
32
number_of_levels
Priority levels in the interrupt controller
2
2
external_
interrupts
Total interrupt pins available for external
system components
12
27
firq_option
Fast-interrupts option
false
false
Actionpoints
+
+
num_actionpoint
Number of trigger events
8
8
aps_feature
Actionpoint feature set
min
min
SmaRT
+
+
smart_stack_
entries
Number of entries in the trace buffer
8
128
smart_
implementation
Flip-flop or memory-based
flip-flop
flip-flop
Performance Monitor
-
+
pct_counters
Number of counters for performance
monitoring
-
8
pct_interrupt
When a counter overflows, an interrupt is
generated
-
true
Real-time trace producer
+
+
rtt_feature_level
'small' - program trace only is available.
`medium' adds data trace. `full' adds core
and aux register trace.
full
full