65
Version 6323-018
Synopsys, Inc.
May 2017
7
System Memory Map
7.1 System Memory Map After a Reset
Following a reset, the memory maps of all AXI masters on the AXC003 CPU Card and on the
ARC SDP Mainboard have to be set up according to the application requirements. Control
registers allow programming the system memory map individually for all AXI masters on the
AXC003 CPU Card and on the ARC SDP Mainboard. These control registers are located in
the local peripheral area of the AXC003 CPU Card and in the peripheral area of the Mainboard.
Following a reset, all CPU cores on the AXC003 CPU Card can access the Mainboard
peripherals in the address range
0xE000_0000
to
0xEFFF_FFFF
and the AXC003 CPU
Card peripherals in the address range
0xF000_0000
to
0xFFFF_FFFF
.
The pre-bootloader programs the corresponding address decoders and, thus, provides the
default memory map. It also initializes the DDR3 SDRAM.
The default memory map programmed by the Pre-Bootloader is described in the
Memory Map After Pre-Bootloader Execution
on page 65.
If needed, alternative memory maps can be programmed for each AXI master individually by
altering the settings of the corresponding control registers. The sections
on page 67 and
on page 108 provide additional information.
7.2 System Memory Map After Pre-Bootloader Execution
The pre-bootloader sets up the memory maps of all AXI masters on the AXC003 CPU Card
and on the ARC SDP Mainboard as shown in Table 25. The memory map has been chosen
to be identical for all AXI masters. See
Example Register Settings for the Default Memory
on page 69 for information on the corresponding register settings.
Table 25
ARC CPU Memory Map After Pre-Bootloader Execution
Master Address
Selected Slave
Slave Address
0xFFFF_FFFF
0xF000_0000
AXI2APB
on AXC003 CPU Card
0x0FFF_FFFF
0x0000_0000
0xEFFF_FFFF
0xE000_0000
AXI2APB
on Mainboard
0x0FFF_FFFF
0x0000_0000
0xDFFF_FFFF
0xD000_0000
AXI Tunnel Slave
for HAPS System
1)
0xDFFF_FFFF
0xD000_0000