40
DesignWare ARC AXC003 CPU Card User Guide
AXC003 Processor FPGA Overview
Synopsys, Inc.
Version 6323-018
May 2017
The ICTL module combines the interrupt requests from the on-chip interrupt sources
into a single interrupt request for each ARC processor.
Dual-core HS38x2 has cross-core interrupts between the cores instantiated in the
inter-core interrupt unit.
The interrupt source responsible for generating the interrupt request can be
determined by reading back the interrupt status register in the GPIO sub-module of
the ICTL.
Interrupts should be cleared within the GPIO sub-module of the ICTL module. The
control signals from the CREG and the CGU are pulses and are thus self-clearing.
Use the GPIO driver for accessing the registers inside the ICTL.
External interrupts
The ICTL module on the Mainboard combines all Interrupt requests from the
Mainboard peripherals into a single signal, which is received by the (top level) GPIO
module on the AXC003 CPU Card. The interrupt output of the GPIO module is
shared between all ARC cores.
In a first step the interrupt handler should read the status register of the ICTL module
on the Mainboard to identify the source peripheral of the interrupt. In a second step
the interrupt status register of the source peripheral provides the primary root cause.
At both intermediate levels (Mainboard ICTL and CPU Card GPIO) the interrupts are
level-sensitive. Interrupts should be cleared within the source peripheral.
The dual-core HS38x2 has an interrupt distribution unit that controls interrupt request
connections from CREG, ICTL, and GPIO.
All interrupts inputs of the ICTL module are edge-sensitive.
on page 42 show the top-level interrupt architecture of the AXC003 Processor FPGA.