Synopsys DesignWare ARC AXC003, User Manual, Page: 138 / 145

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DesignWare ARC AXC003 CPU Card User Guide Detailed Core Configurations
Synopsys, Inc. Version 6323-018
May 2017
Configuration
Option Description HS36 HS38x2
rgf_num_regs
Size (in 32b registers) of the processor
register file
32 32
rgf_num_banks
Number of register banks
1 1
infer_alu_adder
Datapath infer/instantiate
infer infer
infer_mpy_wtree
Datapath infer/instantiate
infer infer
mem_initiator_
ports
0
no access to system memory
2
instruction and data accesses go through
separate interfaces.
1
instruction and data accesses go through a
single interface
1 1
power_domains
Adds isolation and power-switch signal inputs
for use in UPF-base flow when configuring
power domains and generates UPF
constraints
false false
clock_gating
Insert of architectural clock-gating elements
false false
Branch-Prediction Unit
br_bc_entries
Number of entries in the branch cache of the
branch-prediction unit
512 512
br_pt_entries
Number of two-bit predictors in the branch
prediction unit to predict the direction of
conditional branches (taken or not taken)
8192 8192
br_rs_entries
Number of entries in the return-address stack
of the branch-prediction unit.
4 4
br_bc_full_tag
The size of the tag used in the branch cache
of the branch-prediction unit
true true
br_bc_tag_size
If a partial tag is used, this option sets the size
of that tag
4 4
br_tosq_entries
The top-of-stack queue
5 5
br_fb_entries
The size of the buffer that stores fetched
instructions that are not yet executed
2 2
ecc_option
Error checking for on-chip RAMs
none none
grad_entries
Graduation entries track post-commit
instructions awaiting result retirement
8 8
uaux_option
User auxiliary register interface
false false