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DesignWare ARC AXC003 CPU Card User Guide
Clock-Generation Registers
Synopsys, Inc.
Version 6323-018
May 2017
9.1.1.3 TUN_PLL_ODIV Register
31
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
NOUPDATE
BYPASS
EDGE
HIGHTIME
LOWTIME
Address offset: 0x0048
Reset Value:
0x0001_028A
(0x0000_0145 after pre-boot)
Access:
RW
Register for controlling the clock setting for AXI tunnel.
LOWTIME[5:0] sets the amount of time in VCO cycles that the output clock remains low
HIGHTIME[5:0] sets the amount of time in VCO cycles that the output clock remains high
ODIV = L HIGHTIME
OFREQ = VCOFREQ / ODIV
EDGE
chooses the edge that the High Time counter transitions on (0=rising,
1=falling)
BYPASS
bypass the output divider
NOUPDATE
prevents update of the PLL with new settings. Debug only; can be used
for register RW test
To obtain a 50% duty-cycle the divider shall be programmed as follows:
- even divider ratio =>
LOWTIME = HIGHTIME
EDGE =
0
- odd divider ratio
=>
LOWTIME = HI 1
EDGE =
1
9.1.1.4 TUN_PLL_LOCK Register
31
2
1
0
Reserved
ERROR
LOCK
Address offset: 0x0108
Reset Value:
0x0000_0001
Access:
R
Register for Tunnel PLL lock status