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51 

AXC003 Processor FPGA Overview 

DesignWare ARC AXC003 CPU Card User Guide 

 

Version 6323-018 

Synopsys, Inc. 

 

 

May 2017 

Name 

Address Offset 

R/W 

Description 

ARC CPU Address Decoder Registers 

CPU_A_SLV_SEL0 

0x0000_1020    RW 

Slave select register for ARC 
CPU 

CPU_A_SLV_SEL1 

0x0000_1024   RW 

Slave select register for ARC 
CPU 

CPU_A_SLV_OFFSET0 

0x0000_1028   RW 

Address offset register for 
ARC CPU 

CPU_A_SLV_OFFSET0 

0x0000_102C   RW 

Address offset register for 
ARC CPU 

CPU_A_UPDATE 

0x0000_1034 

RW1C 

Address decoder update 
register for ARC CPU 

RTT Address Decoder Registers 

RTT_A_SLV_SEL0 

0x0000_1040    RW 

Slave select register for RTT  

RTT_A_SLV_SEL1 

0x0000_1044   RW 

Slave select register for RTT 

RTT_A_SLV_OFFSET0 

0x0000_1048   RW 

Address offset register for RTT 

RTT_A_SLV_OFFSET0 

0x0000_104C   RW 

Address offset register for RTT 

RTT_A_UPDATE 

0x0000_1054 

RW1C 

Address decoder update 
register for RTT 

Physical Address Extensions Registers 

CREG_PAE 

0x0000_1060   RW 

PAE register 

CREG_PAE_UPDATE 

0x0000_1074 

RW1C 

PAE update register  

CPU Start Registers 

CPU_START 

0x0000_1400 

RW 

ARC CPU start register 

CPU_0_ENTRY 

0x0000_1404 

RW 

ARC CPU-0 kernel entry point 
register 

CPU_1_ENTRY 

0x0000_1408 

RW 

ARC CPU-0 kernel entry point 
register 

CPU_BOOT 

0x0000_1010 

RW 

ARC CPU boot register 

Summary of Contents for DesignWare ARC AXC003

Page 1: ...DesignWare ARC AXC003 CPU Card User Guide Version 6323 018 May 2017...

Page 2: ...rohibited It is the reader s responsibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WI...

Page 3: ...17 4 2 Core Selection 17 ARC HS36 CPU 18 ARC HS34 CPU 18 ARC HS38 Core 0 18 ARC HS38 Core 1 18 5 Self Tests 19 5 1 Self Test Overview 19 5 2 Executing the Self Test of the ARC HS36 Core 22 5 3 Executi...

Page 4: ...Default Memory Map 69 7 4 Memory Map of the Local Peripherals 71 8 Programmer s Reference 72 8 1 Supported Tools and Operating Systems 72 8 2 Boot Modes 72 Common Boot Modes 72 ARC HS36 Booting from...

Page 5: ...CPU Update Register 119 9 4 ARC RTT Address Decoder Registers 120 RTT_A_SLV0 ARC RTT Slave Select Register 0 120 RTT_A_SLV1 ARC RTT Slave Select Register 1 120 RTT_A_OFFSET0 ARC RTT Address Offset Reg...

Page 6: ...6 DesignWare ARC AXC003 CPU Card User Guide Contents Synopsys Inc Version 6323 018 May 2017 Glossary and References 144 Glossary 144 References 145...

Page 7: ...ntrol LEDs on the AXC003 CPU Card 32 Location of the User LEDs on the AXC003 CPU Card 32 Location of the Pushbutton on the AXC003 CPU Card 34 AXC003 Memory Map 37 AXC003 I O Coherency Architecture 38...

Page 8: ...Command Line Options 91 Debugger Options Target Selection 92 Specifying a Path to the elf File 92 Debugger Status 93 HyperTerminal Output 94 DIP Switch Settings for Autonomous Code Execution on the AR...

Page 9: ...Usage of the CPU Start Buttons of the ARC SDP Mainboard 63 Table 24 Control Bits of the CPU LEDs on the ARC SDP Mainboard 64 Table 25 ARC CPU Memory Map After Pre Bootloader Execution 65 Table 26 AXI...

Page 10: ...ackage contains the following items DesignWare ARC AXC003 CPU Card mounted on ARC SDP Mainboard 100 240V AC power adapter including power cables for U S UK and EU outlets USB cable Pen sized plastic d...

Page 11: ...Version 6323 018 Synopsys Inc May 2017 1 2 DesignWare ARC AXC003 CPU Card Standalone The DesignWare ARC AXC003 CPU Card package contains the DesignWare ARC AXC003 CPU Card printed circuit board Design...

Page 12: ...mplete AXS103 Software Development Platform 2 2 Performing a Self Test Follow these steps to get the AXS103 Software Development Platform up and running and to perform a self test 1 Download and unzip...

Page 13: ...rd is now configured automatically and the Mainboard executes the reset sequence The status LEDs DONE RESET TUNNEL0 and TUNNEL1 on the Mainboard shine red during startup 6 Wait until all status LEDs e...

Page 14: ...ores as described in the Self Tests section on page 19 For the next steps see Bare Metal Package on page 78 Note The AXS103 Software Development Platform is supplied with the ARC SDP Mainboard version...

Page 15: ...CPU Card and the default boot mode settings for the cores on the AXC003 CPU Card which can be selected by DIP switches on the ARC SDP Mainboard 3 1 Default Jumper Settings on the AXC003 CPU Card The...

Page 16: ...bypassed If you want to start an ARC core manually set bit 7 boot start mode to the right side position In this case the CPU delays code execution after reset until the corresponding CPU Start button...

Page 17: ...he reset state SW802 on the AXC003 CPU Card defines the FPGA image to be loaded at power on reset The following bits of SW802 define the FPGA image that is selected 00 FPGA image for ARC HS36 CPU 01 F...

Page 18: ...Bit 6 of SW2501 0 Bits 1 to 2 of SW2503 1 2 00 ARC HS34 CPU To select ARC HS34 use following settings SW802 00 Bit 6 of SW2501 1 Bits 1 to 2 of SW2503 1 2 00 ARC HS38 Core 0 To select ARC HS38 core 0...

Page 19: ...U Card are set as described in Default Board Settings on page 15 The steps described in Getting Started on page 12 have been performed Note If you have programmed other applications in the SPI Flash y...

Page 20: ...the PC Additionally the current CPU core speed is measured and displayed in the debug console For a quick start use a hyperterminal such as PuTTY as a debug console see Getting Started Next the self t...

Page 21: ...PU Card The seven segment displays on the ARC SDP Mainboard show the characters listed in Table 2 The number indicates the ARC core that is currently running Table 2 Characters on the Seven Segment Di...

Page 22: ...ing the Self Test of the ARC HS36 Core Follow the steps described below to perform the self test of the ARC HS36 core 1 Connect the ARC SDP Mainboard to your PC using the USB cable which must be conne...

Page 23: ...LEDs and the LED0121x LEDs 8 Push the reset button on the ARC SDP Mainboard to stop the test Location of the RESET Button on the ARC SDP Mainboard 5 3 Executing the Self Test of the ARC HS38x2 Core Fo...

Page 24: ...Inc Version 6323 018 May 2017 Location of the ARC SDP Mainboard s Power Supply and Power Switch 3 Launch PuTTY on your computer 4 Push the CPU Start button SW2504 on the ARC SDP Mainboard Location of...

Page 25: ...Self Test 7 Observe the walking patterns shown by the CPU LEDs and the LED0121x LEDs 8 Push the reset button on the ARC SDP Mainboard to stop the test Location of the RESET Button on the ARC SDP Main...

Page 26: ...ad webpage 4 and install the axs_comm tool as described in the ARC SDP Mainboard User Guide 5 2 Download and unzip the axs103_selftest_firmware_ version zip file from the ARC SDP download webpage 4 3...

Page 27: ...includes a 2 GByte DDR3 SDRAM 256 KByte local SRAM physically implemented inside the FPGA and internal ROM physically implemented as additional 32 KByte local SRAM inside the FPGA The internal ROM ar...

Page 28: ...Controller CGU GPIO AXI Tunnel DDR3 Controller 256 kByte SRAM 2 GByte DDR2 AXC003 CPU Card FPGA AXI APB I T T T T T FPGA Flash 16 MByte AXI Interconnect ARC HS36 core I I Instr Data Real Time Trace E...

Page 29: ...ler CGU GPIO AXI Tunnel DDR3 Controller 256 kByte SRAM 2 GByte DDR2 AXC003 CPU Card FPGA AXI APB I T T T T T FPGA Flash 16 MByte ARC HS38x2 core I I Real Time Trace ETM Mictor38 Jumpers Ashling Lauter...

Page 30: ...r is supplied to the AXC003 CPU Card by the ARC SDP Mainboard through the power supply connector on the bottom of the AXC003 CPU Card board The following voltage levels are provided 1 1V 1 8V 2 5V 3 3...

Page 31: ...d P_ETM2 The P_ETM1 connector can be used to connect an Ashling Ultra XD debugger to ARC JTAG chain The ARC JTAG connection is controlled by the JP1207 jumper setting it is described in Table 3 on pag...

Page 32: ...oltage In normal operation all six LEDs shine green The location of these LEDs is shown in Figure 20 Location of the Power Control LEDs on the AXC003 CPU Card The location of the user LEDs on the AXC0...

Page 33: ...03 CPU Card The LED is ON when this bit is set to 1 SWPORTB_DR 11 Connected to LED3 on the AXC003 CPU Card The LED is ON when this bit is set to 1 SWPORTB_DR 12 Connected to LED4 on the AXC003 CPU Car...

Page 34: ...even Segment Displays The AXC003 CPU Card features two seven segment displays which are controlled by a field of the SWPORTB_DR register as listed in Table 5 on page 35 The register is located at the...

Page 35: ...he display is ON when its control bit is set to 1 SWPORTB_DR 31 24 Controls the lower seven segment display A segment of the display is ON when its control bit is set to 1 6 7 AXC003 Processor FPGA Ov...

Page 36: ...e 5 instruction fetch buffer 2 Radix 4 hardware divider Real time clock Real time trace 32x32 multiply Dual and quad MAC SIMD instructions Timer0 Timer1 Load Store Unit LLOCK SCOND instructions Branch...

Page 37: ...ess range In the AXC003 the PAE functionality is used to extend the physical address range from 4 to 8 GByte A high level overview of the memory map is shown in Figure 23 The memory map for the lower...

Page 38: ...the I O coherency port is filtered by the IOC bridge based on its address When it falls within a certain programmable address window the traffic is forwarded to the SCU When it fails outside the addre...

Page 39: ...offset 6 slv ioc offset 7 slv ioc offset 15 0x1_0000_0000 0x1_8000_0000 0x1_FFFF_FFFF MSB of physical address ignored by DMA client 0 slv ioc offset 14 slv ioc offset 15 Interrupts GPIO interrupts ar...

Page 40: ...he ICTL module on the Mainboard combines all Interrupt requests from the Mainboard peripherals into a single signal which is received by the top level GPIO module on the AXC003 CPU Card The interrupt...

Page 41: ...41 AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Version 6323 018 Synopsys Inc May 2017 HS36 Interrupt Architecture...

Page 42: ...errupt Architecture Each ARC core is configured with 8 external interrupt inputs The interrupt mapping of the two ARC cores is listed in Table 7 on page 43 and Table 8 on page 44 Table 9 on page 45 sh...

Page 43: ...ard peripherals The interrupt request is received by the ICTL module on the Mainboard and the GPIO register EXT_PORTA 12 on the AXC003 CPU Card See Table 9 25 Interrupt from interrupt controller on AX...

Page 44: ...24 Combined interrupt from Mainboard peripherals The interrupt request is received via the ICTL module on the Mainboard and the GPIO register EXT_PORTA 12 on the AXC003 CPU Card See Table 9 25 Interr...

Page 45: ...ource 0 Mainboard CGU PLL lock interrupt 1 Mainboard CGU PLL unlock interrupt 2 Mainboard CGU PLL lock error interrupt 3 Mainboard CREG interrupt 4 Ethernet interrupt 5 PGU interrupt 6 NAND interrupt...

Page 46: ...to the CGU The CGU generates all the internal clocks using the internal PLLs and clock dividers of the FPGA The main clock domains are highlighted by the different colors in Figure 28 The AXC003 Proce...

Page 47: ...47 AXC003 Processor FPGA Overview DesignWare ARC AXC003 CPU Card User Guide Version 6323 018 Synopsys Inc May 2017 Clock Architecture...

Page 48: ...in that serves as an active low hardware reset When the external hardware reset is active the entire FPGA is reset This pin is routed to the HapsTrak II connector and controlled by reset circuitry on...

Page 49: ...3 Processor FPGA the JTAG ports of the different ARC cores are daisy chained into a JTAG chain where the data output from the first core becomes the data input to the second core and so forth the cont...

Page 50: ...Memory Map Name Address Offset R W Description Clock Generation Registers TUN_PLL_IDIV 0x0000_0040 RW Tunnel input divider register TUN_PLL_FBIDIV 0x0000_0044 RW Tunnel feedback divider register TUN_P...

Page 51: ...U RTT Address Decoder Registers RTT_A_SLV_SEL0 0x0000_1040 RW Slave select register for RTT RTT_A_SLV_SEL1 0x0000_1044 RW Slave select register for RTT RTT_A_SLV_OFFSET0 0x0000_1048 RW Address offset...

Page 52: ...4 describes the function of the GPIO bits Table 13 GPIO Register Memory Map Name Address Offset R W Description GPIO_SWPORTA_DR 0x3000 R W Port A Data Register Controls LEDs on the ARC SDP Mainboard G...

Page 53: ...hen this bit is set to 1 14 12 Reserved 15 Connected to LED2507 of the ARC SDP Mainboard The LED is ON when this bit is set to 1 16 Connected to LED2508 of the ARC SDP Mainboard The LED is ON when thi...

Page 54: ...CPU Card The LED is ON when this bit is set to 1 11 Connected to LED3 on the AXC003 CPU Card The LED is ON when this bit is set to 1 12 Connected to LED4 on the AXC003 CPU Card The LED is ON when this...

Page 55: ...reserved 2 Connected to JP1202 usage reserved 3 Connected to JP1203 usage reserved 4 Connected to JP1204 usage reserved 5 Connected to JP1205 usage reserved 6 Connected to JP1206 usage reserved 7 Conn...

Page 56: ...core has internal ICCM and DCCM memories The locations of these memories depend on register settings in the ARC HS36 core The pre boot loader keeps the ICCM at its reset address 0x1000_0000 but moves...

Page 57: ...XC003 software package The GPIO pin located at SW2501 6 defines whether data cache and instruction cache are used This pin does not change hardware configuration and it is used by the pre bootloader s...

Page 58: ...lowing voltage levels are provided 1 1V 1 8V 2 5V 3 3V and 12 0V Table 20 provides a pin description of the power supply connector Table 20 Pinout of the Power Supply Connector Pin Name Description 1...

Page 59: ...esources of the ARC SDP Mainboard and drives all audio input signals of the Mainboard at the HapsTrak II Connector to their inactive state 6 11 Usage of ARC SDP Mainboard Resources Usage of the Mainbo...

Page 60: ...on Boot Mirror 00 Disabled 01 Internal ROM 10 Reserved 11 Reserved 2 3 Bypass loading Switch Position Pre bootloader Mode 0 Pre bootloader bypasses loading application from SPI flash Only default init...

Page 61: ...lect Switch Position Boot Core 1 2 00 HS38x2_0 or HS36 1 2 01 HS38x2_1 010 Reserved 011 Reserved 2 4 Multicore mode Switch Position Multicore mode 00 Single core 01 Dual core 10 Reserved 11 Reserved 5...

Page 62: ...ORTA 22 Reserved GPIO EXT_PORTA 23 Cache mode HS34 HS36 only Boot start mode Reserved The DIP switch settings shown in Figure 33 are the factory default settings All cores are configured to boot from...

Page 63: ...ding CPU Start button can be used for application purposes This is however not recommended A CPU Start button should only be used for application purposes when the corresponding core is not configured...

Page 64: ...PU LEDs on the ARC SDP Mainboard Control Bit Description SWPORTA_DR 0 Controls LED2501 SWPORTA_DR 1 Controls LED2502 SWPORTA_DR 5 Controls LED2503 SWPORTA_DR 6 Controls LED2504 SWPORTA_DR 10 Controls...

Page 65: ...efault memory map programmed by the Pre Bootloader is described in the System Memory Map After Pre Bootloader Execution on page 65 If needed alternative memory maps can be programmed for each AXI mast...

Page 66: ...of the individual memory map settings on the AXC003 CPU Card and the ARC SDP Mainboard with the AXI Tunnel between the AXC003 CPU Card and the ARC SDP Mainboard abstracted away The ARC HS36 core has...

Page 67: ...e AXC003 CPU Card Control registers are available for each AXI master for each core and for the AXI tunnel to customize its memory map The full 4 GByte AXI memory map is partitioned into 16 address ap...

Page 68: ...perture number The memory map as seen by the AXI2APB bridge is described in Memory Map of the Local Peripherals on page 71 Setting Up the AXI Masters on the ARC SDP Mainboard The address map of the AX...

Page 69: ...CFFF_FFFF 0xC000_0000 0 0x0 Unused 11 0xBFFF_FFFF 0xB000_0000 1 0x3 DDR3 SDRAM 0x3FFF_FFFF 0x0000_0000 10 0xAFFF_FFFF 0xA000_0000 1 0x2 9 0x9FFF_FFFF 0x9000_0000 1 0x1 8 0x8FFF_FFFF 0x8000_0000 1 0x0...

Page 70: ..._FFFF 0xB000_0000 1 0xB TUNNEL0 CPU Card 0xBFFF_FFFF 0xB000_0000 10 0xAFFF_FFFF 0xA000_0000 1 0xA 0xAFFF_FFFF 0xA000_0000 9 0x9FFF_FFFF 0x9000_0000 1 0x9 0x9FFF_FFFF 0x9000_0000 8 0x8FFF_FFFF 0x8000_0...

Page 71: ...shows the address offsets of the individual peripherals and the corresponding aperture within the AXI2APB section This means that the address offset listed in Table 32 has to be added to the base add...

Page 72: ...can start executing the boot code Each of the ARC cores can be started individually in one of the four following ways Starting the ARC core with the debugger Starting the ARC core using a CPU Start b...

Page 73: ...3 Download code into the configured boot source i e into the SPI Flash 4 Start the ARC core by pushing the corresponding CPU Start button on the Mainboard ARC HS36 Booting from ICCM0 The ARC HS36 core...

Page 74: ...Boot Overview The AXS103 Software Development Platform includes a set of pre bootloaders which are functionally identical but compiled for the different cores The pre bootloader performs two main task...

Page 75: ...ge in the SPI flash Loading an image can be bypassed by setting bit SW2501 3 to 0 In that case the pre bootloader does not load any image but only performs a board initialization and sets the ARC core...

Page 76: ...so used in the debugger as listed in Table 33 If loading of an image is bypassed SW2501 3 a dot is displayed next to the CPU number The right character shows an error code as explained in Table 34 on...

Page 77: ...pying the image to the target memory location the calculated CRC differs from the one in the header blank When the right character is blank off but the left character shows a digit the pre bootloader...

Page 78: ...version zip This zip file is available on the ARC SDP download webpage 4 After unzipping this file you can find MQX related files in the software mqx mqx_version directory Some examples for using MQX...

Page 79: ...ontains all basic drivers for the AXS103 Software Development Platform See the Drivers for Bare Metal Applications on page 77 for details project This folder contains the files related to the gmake bu...

Page 80: ...DE Select Workspace Directory 2 Open the workspace and select File Import from the top menu 3 Expand the General folder then select Existing Projects into Workspace and click the Next button MetaWare...

Page 81: ...uilt for code execution from DDR AXS_MEMORY_TYPE ddr console UART via USB data port AXS_CONSOLE_TPYE usb_uart If you wish to set other options edit the file software baremetal project_arcmw axs103 com...

Page 82: ...the project s using any of the following methods Right click the selected project s again and select Build Project Select Build Project from the Project menu Enter CTRL B You can see the build results...

Page 83: ...cation core archs36 Select ARC HS36 core archs38 Select ARC HS38 core console uart0 Debug console is connected to the UART0 interface at the DB9 connector 1 or at the Pmod connector 1 2 uart1 Debug co...

Page 84: ...n file for SPI Flash or SD Card hex Hex file map Map file Two sets of files are generated One set includes hostlink the other doesn t For the set with hostlink the string _hostlink is appended to the...

Page 85: ...ample application in a debugger 1 Set the jumpers to their default settings see Jumpers on page 31 The JTAG interface is in daisy chained mode Settings of the DIP Switches on the ARC SDP Mainboard for...

Page 86: ...the jumpers JP2309 and JP2310 Location of the Debug Interfaces and the Corresponding Jumpers 4 Switch on the power supply or push the RESET button Location of the ARC SDP Mainboard s Power Supply and...

Page 87: ...e AXS103 Software Development Platform is ready for loading and executing your application Running a Bare Metal Application in the MetaWare IDE Debugger After you successfully build the C Project you...

Page 88: ...guration 7 Select the Main tab and enter a name of your choice in the Name field It is best to compose the name from the project name and the ARC core 8 Enter the name of the ELF file with or without...

Page 89: ...ns set a property to select the correct core and device prop cpunum 1 Select ARC HS34 core prop cpunum 1 Select ARC HS36 core prop cpunum 1 Select ARC HS38x2 core 1 prop cpunum 2 Select ARC HS38x2 cor...

Page 90: ...This example assumes that the application hello_uart has been built for execution from the DDR3 SDRAM The result of building is a file with the extension elf Use this file for the debugger 1 Perform t...

Page 91: ...tion prop cpunum 1 Select ARC HS36 core prop cpunum 1 Select ARC HS38x2 core 1 prop cpunum 2 Select ARC HS38x2 core 2 If you are using a Digilent probe rather than the USB data port set one of the fol...

Page 92: ...Debug a process or processes window select the correct elf file and press OK Specifying a Path to the elf File The debugger is now ready for executing the image In the auxiliary register AUX0004 the A...

Page 93: ...93 Bare Metal Package DesignWare ARC AXC003 CPU Card User Guide Version 6323 018 Synopsys Inc May 2017 Debugger Status...

Page 94: ...ctions marked with yellow highlighting Only images without HOSTLINK should be programmed in the SPI Flash 1 After building the image use the axs_comm exe tool to store the image in the SPI flash First...

Page 95: ...Restoring the Self Tests in the SPI Flash on page 25 Note When flashing an image into SPI flash the axs_comm tool prefixes the BIN file with a 256 byte header Hence the total size occupied by an image...

Page 96: ...the MQX package make sure that you have installed the MetaWare toolchain compiler linker debugger This is a separate product which is not part of the AXS103 Software Development Platform Overview The...

Page 97: ...tes usage of AXC003 seven segment indicator and LEDs axs103 selftest self test application axs103 eping demonstrates use of the Ethernet device driver API build This folder contains configuration file...

Page 98: ...36 bat for ARC HS36 These batch files invoke the MetaWare debugger with the required options either to run the application or to start the GUI for debugging 4 Add the MQX_ROOT build axs103 to the PATH...

Page 99: ...ct which is not part of the AXS103 Software Development Platform You can find the latest information about how to download Linux and U Boot sources and build binary images you can find in the article...

Page 100: ...to Serial and the Speed to 115200 Additionally you may connect USB keyboard to the USB port on the board Ethernet cable HDMI Monitor Executing the Linux Image with U Boot You can use the U Boot bootl...

Page 101: ...o EEPROM with the saveenv command 8 7 3 2 Linux Execution with U Boot Started Manually To run a Linux image from the SD card do the following 1 Rename the uImage_axs103 file to uImage 2 Copy uImage to...

Page 102: ...ed node frame_buffer be000000 compatible id shared dma pool percpu Embedded 6 pages cpu 9fd64000 s16384 r8192 d24576 u49152 Built 1 zonelists in Zone order mobility grouping on Total pages 65248 Kerne...

Page 103: ...Registered protocol family 16 irq no irq domain found for cpu_card dw apb gpio 0x2000 gpio controller 0 SCSI subsystem initialized usbcore registered new interface driver usbfs usbcore registered new...

Page 104: ...tmmac 0 01 active ehci_hcd USB 2 0 Enhanced Host Controller EHCI Driver ehci platform EHCI generic platform driver ehci platform e0040000 ehci EHCI Host Controller ehci platform e0040000 ehci new USB...

Page 105: ...discover stmmaceth e0018000 ethernet eth0 Link is Up 100Mbps Full flow control off udhcpc sending discover udhcpc sending discover udhcpc no lease failing FAIL ssh keygen generating new host keys RSA...

Page 106: ...e RESET button SW2410 on the Mainboard You see following log in serial console AXS PREBOOT Apr 14 2017 13 44 39 ARCHS38 0 53 CPU FPGA VERSION 1342017 15 10 MB FPGA VERSION 1442017 13 21 MB CPLD VERSIO...

Page 107: ...board to run Linux To prevent Linux autostart press any key within three seconds to stop the countdown Cleaning To clean bootcmd variable run following commands setenv bootcmd saveenv 8 8 ARCv2 Instru...

Page 108: ...3Mhz Minimum input clock frequency is 10MHz VCO range for Tunnel PLL is 600 1440MHz 9 1 1 1 TUN_PLL_IDIV Register 31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NOUPDATE BYPASS EDGE HIGHTIME LOWTIM...

Page 109: ...set 0x0044 Reset Value 0x0000_03CF 0x0000_03CF after pre boot Access RW Register to control setting of the Tunnel PLL feedback divider LOWTIME 5 0 sets the amount of time in VCO cycles that the feedba...

Page 110: ...low HIGHTIME 5 0 sets the amount of time in VCO cycles that the output clock remains high ODIV LOWTIME HIGHTIME OFREQ VCOFREQ ODIV EDGE chooses the edge that the High Time counter transitions on 0 ris...

Page 111: ...3 2 1 0 Reserved NOUPDATE BYPASS EDGE HIGHTIME LOWTIME Address offset 0x0080 Reset Value 0x0000_2041 0x0000_3001 after pre boot Access RW Register to control setting of the ARC PLL input divider LOWTI...

Page 112: ...GHTIME 5 0 sets the amount of time in VCO cycles that the feedback clock remains high FBDIV LOWTIME HIGHTIME VCOFREQ 33MHz IDIV FBDIV EDGE chooses the edge that the High Time counter transitions on 0...

Page 113: ...ng BYPASS bypass the output divider NOUPDATE prevents update of the PLL with new settings Debug only can be used for register RW test To obtain a 50 duty cycle the divider shall be programmed as follo...

Page 114: ...RW 1 Slave select for address aperture 0 0 no slave selected 1 slave 1 selected DDR controller 2 slave 2 selected SRAM controller 3 slave 3 selected AXI tunnel 4 slave 4 selected AXI2APB bridge 5 sla...

Page 115: ...elect for address aperture 11 1 19 16 SLV_SEL12 RW 1 6 Slave select for address aperture 12 1 23 20 SLV_SEL13 RW 1 6 Slave select for address aperture 13 1 27 24 SLV_SEL14 RW 1 6 Slave select for addr...

Page 116: ...B 15 15 256MB 7 4 SLV_OFFSET9 RW 1 9 Address offset for address aperture 9 1 11 8 SLV_OFFSET10 RW 2 10 Address offset for address aperture 10 1 15 12 SLV_OFFSET11 RW 3 11 Address offset for address ap...

Page 117: ...ess Value Description 3 0 SLV_SEL0 RW Slave select for address aperture 0 0 no slave selected 1 slave 1 selected DDR controller 2 slave 2 selected SRAM controller 3 slave 3 selected AXI tunnel 4 slave...

Page 118: ...lect for address aperture 11 1 19 16 SLV_SEL12 RW 0 Slave select for address aperture 12 1 23 20 SLV_SEL13 RW 3 Slave select for address aperture 13 1 27 24 SLV_SEL14 RW 3 Slave select for address ape...

Page 119: ...r address aperture 9 1 11 8 SLV_OFFSET10 RW 2 Address offset for address aperture 10 1 15 12 SLV_OFFSET11 RW 3 Address offset for address aperture 11 1 19 16 SLV_OFFSET12 RW 0 Address offset for addre...

Page 120: ...bridge 5 slave 5 selected ROM Controller 6 slave 6 selected IOC port 7 Reserved 7 4 SLV_SEL1 RW 1 Slave select for address aperture 1 1 11 8 SLV_SEL2 RW 1 Slave select for address aperture 2 1 15 12...

Page 121: ...Slave select for address aperture 14 1 31 28 SLV_SEL15 RW 1 Slave select for address aperture 15 1 2 Same encoding as SLV_SEL8 RTT_A_OFFSET0 ARC RTT Address Offset Register 0 Address offset 0x1048 Res...

Page 122: ...Address offset for address aperture 11 1 19 16 SLV_OFFSET12 RW 4 Address offset for address aperture 12 1 23 20 SLV_OFFSET13 RW 5 Address offset for address aperture 13 1 27 24 SLV_OFFSET14 RW 6 Addr...

Page 123: ...xtension bits for 5 th 256MByte 1 10 PAE_5 RW 0 Physical address extension bits for 6 th 256MByte 1 12 PAE_6 RW 0 Physical address extension bits for 7 th 256MByte 1 14 PAE_7 RW 0 Physical address ext...

Page 124: ...he ARC SDP Mainboard Table 18 CPU_START Register Legend reset value Bit Name Access Value Description 0 START_0 RW1C 0x0 Writing a 1 to this bit will generate a cpu_start pulse for the 1st ARC 1 START...

Page 125: ...00 Table 19 CPU_0_ENTRY Register Legend reset value Bit Name Access Value Description 31 0 ENTRY RW 0 Kernel entry point for ARC CPU 0 CPU_1_ENTRY ARC CPU 1 Kernel Entry Point Register Address offset...

Page 126: ...led from SW2501 2 1 pin during power on reset 2 Reset value for IMAGE_SRC 1 0 is sampled from SW2501 4 3 pin during power on reset 3 Reset value for MODE_HS34 is sampled from SW2501 6 pin during power...

Page 127: ...put Register GPIO_SWPORTA_DR Legend reset value Bit Name Access Value Description 0 MB_LED2501 RW 0x0 LED2501 on the ARC SDP Mainboard is OFF 0x1 LED2501 on the ARC SDP Mainboard is ON 1 MB_LED2502 RW...

Page 128: ...ame Access Value Description 7 0 Reserved RW 0x0 8 LED0 RW 0 LED0 on the AXC003 CPU Card is OFF 1 LED0 on the AXC003 CPU Card is ON 9 LED1 RW 0 LED1 on the AXC003 CPU Card is OFF 1 LED1 on the AXC003...

Page 129: ...n when its control bit is set to 1 GPIO_EXT_PORTA GPIO Port A Input Register Address offset 0x3050 Reset value 0x00FD_0000 Table 43 GPIO Port A Input Register GPIO_EXT_PORTA Legend reset value Bit Nam...

Page 130: ...utton SW2505 on the ARC SDP Mainboard not pressed 23 MB_SW2507 R 0x0 CPU Start button SW2507 on the ARC SDP Mainboard pressed 0x1 CPU Start button SW2507 on the ARC SDP Mainboard not pressed 31 24 R 0...

Page 131: ...s DesignWare ARC AXC003 CPU Card User Guide Version 6323 018 Synopsys Inc May 2017 1 Reserved 7 JP1207 R 0 Default setting 1 1 Reserved 31 8 Reserved R 0 1 Reset value depends on jumper settings on th...

Page 132: ...mount the AXC003 CPU Card on an ARC SDP Mainboard 1 Make sure that the ARC SDP Mainboard is switched off 2 Mount the AXC003 CPU Card on the ARC SDP Mainboard and make sure that the Power Supply Connec...

Page 133: ...Mirror Select Bypass loading Reserved SW2503 1 3 4 5 6 7 1 0 Boot Core Select Multi core mode 8 Reserved 2 9 SW2502 1 2 3 4 5 6 7 1 0 Reserved SW2401 1 3 4 5 6 7 1 0 For application purposes 8 2 9 10...

Page 134: ...e interested in the console output of the built in self test 1 Download putty exe from http www putty org 2 Make sure that you have connected the USB cable to your computer and that the USB device dri...

Page 135: ...018 Synopsys Inc May 2017 Identification of COM Port 5 Execute putty exe The PuTTY Configuration window appears 6 Set the Connection type to Serial 7 Enter the name of the COM port in the Serial line...

Page 136: ...136 DesignWare ARC AXC003 CPU Card User Guide Installing and Configuring PuTTY Synopsys Inc Version 6323 018 May 2017 PuTTY Configuration 9 Click on Open to launch the PuTTY terminal...

Page 137: ...CNUM 5 0 instances The number of instantiations of this core 1 2 ARCv2HS halt_on_reset The core is halted initially on reset true true byte_order The endianness of the core little little atomic_option...

Page 138: ...of architectural clock gating elements false false Branch Prediction Unit br_bc_entries Number of entries in the branch cache of the branch prediction unit 512 512 br_pt_entries Number of two bit pre...

Page 139: ...troller 2 2 external_ interrupts Total interrupt pins available for external system components 12 27 firq_option Fast interrupts option false false Actionpoints num_actionpoint Number of trigger event...

Page 140: ...when configuring power domains false false Memory Protection Unit mpu_num_regions Number of configured memory regions 8 Memory Management Unit mmu_ntlb_num_entr ies Number of joint TLB normal page en...

Page 141: ...ways 2 4 ic_bsize Cache line length in bytes 32 64 ic_disable_on_ reset Instruction cache is disabled on reset false false ic_pipeline_bus Insert a pipeline register on the instruction cache s refill...

Page 142: ...ss CCMs from external bus devices AXI AXI biu_dmi_bus_data_ w Data width of the DMI busses 64 64 biu_ioc_bus_num The number of I O coherency busses 0 1 biu_ioc_bus_axi_ idw This specifies the AXI ID w...

Page 143: ...ne ARConnect mcip_has_intrpt Inter core interrupt unit true mcip_has_sema Inter core semaphore unit true mcip_sema_num The number of semaphores 16 mcip_has_msg_sram Inter core message unit true mcip_m...

Page 144: ...or Unit DDR3 Double Data Rate 2 GPIO General Purpose Input Output HW Hardware HAPS High performance ASIC Prototyping System FPGA based prototyping system of Synopsys HapsTrak II Standard SAMTEC connec...

Page 145: ...ndom Access Memory SRAM Static Random Access Memory SW Software References 1 HapsTrak II standard 2 C C Programmer s Guide for the MetaWare Compiler 3 Synopsys DesignWare dw_apb_gpio Databook http www...

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