115
AXI Tunnel Address Decoder Registers
DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018
Synopsys, Inc.
May 2017
Table 2
TUN_A_SLV1 Register
Legend: * reset value
Bit
Name
Access Value Description
3:0
SLV_SEL8
RW
1 / 6*
Slave select for address aperture[8]
*
0
no slave selected
1
slave 1 selected (=> DDR controller)
2
slave 2 selected (=> SRAM controller)
3
slave 3 selected (=> AXI tunnel)
4
slave 4 selected (=> AXI2APB bridge)
5
slave 5 selected (=> ROM Controller)
6
slave 6 selected (=> IOC port)
7
Reserved
7:4
SLV_SEL9
RW
1 / 6*
Slave select for address aperture[9]
1)
11:8
SLV_SEL10
RW
1 / 6*
Slave select for address aperture[10]
1)
15:12
SLV_SEL11
RW
1 / 6*
Slave select for address aperture[11]
1)
19:16
SLV_SEL12
RW
1 / 6*
Slave select for address aperture[12]
1)
23:20
SLV_SEL13
RW
1 / 6*
Slave select for address aperture[13]
1)
27:24
SLV_SEL14
RW
1 / 6*
Slave select for address aperture[14]
1)
31:28
SLV_SEL15
RW
1 / 6*
Slave select for address aperture[15]
1)
1) Same encoding as SLV_SEL8
TUN_A_OFFSET0: AXI Tunnel Address Offset Register 0
Address offset:
0x1008
Reset value:
0x7654_3210
Table 3
TUN_A_OFFSET0 Register
Legend: * reset value
Bit
Name
Access Value Description
3:0
SLV_OFFSET0
RW
Address offset select for address aperture[0]
0*
0*256MB
1
1*256MB
…
…
15
15*256MB
7:4
SLV_OFFSET1
RW
1*
Address offset for address aperture[1]
1)
11:8
SLV_OFFSET2
RW
2*
Address offset for address aperture[2]
1)
15:12
SLV_OFFSET3
RW
3*
Address offset for address aperture[3]
1)
19:16
SLV_OFFSET4
RW
4*
Address offset for address aperture[4]
1)