Synopsys DesignWare ARC AXC003, User Manual, Page: 44 / 145

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DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview
Synopsys, Inc. Version 6323-018
May 2017
Table 8 Interrupt Mapping for ARC HS38
Interrupt
# Interrupt source Remarks
0
ARC internal interrupt reset
1
memory error
2
instruction error
16
timer0
17
timer1
18
Reserved
19
Cross-core Interrupt The interrupt request from Inter-core Interrupt
Unit
20
ARC internal interrupt Performance counter
21
Reserved
22
23
24
Combined interrupt
from Mainboard
peripherals The interrupt request is received via the ICTL
module on the Mainboard and the GPIO register
EXT_PORTA[12] on the AXC003 CPU Card.
See Table 9 .
25
Interrupt from interrupt
controller on AXC003
CPU Card Note that interrupts that are edge-sensitive within
the ICTL should also be cleared at the ICTL
level.
ICTL
bit
Description Sensitivity
0 Tunnel parity error level
1 Address decoder
updated edge
2 UART level
3 PLL locked edge
4 PLL unlocked edge
5 PLL lock error edge
26
CREG Configurable interrupt request from AXC003
CREG
27
CREG Configurable interrupt request from AXC003
CREG