Synopsys DesignWare ARC AXC003, User Manual, Page: 113 / 145

113
Clock-Generation Registers DesignWare ARC AXC003 CPU Card User Guide
Version 6323-018 Synopsys, Inc.
May 2017
Register for controlling the clock setting for the ARC CPU
LOWTIME[5:0] sets the amount of time in VCO cycles that the output clock remains low
HIGHTIME[5:0] sets the amount of time in VCO cycles that the output clock remains high
ODIV = L HIGHTIME
OFREQ = VCOFREQ / ODIV
EDGE chooses the edge that the High Time counter transitions on (
0
=rising,
1
=falling)
BYPASS bypass the output divider
NOUPDATE prevents update of the PLL with new settings. Debug only; can be used
for register RW test
To obtain a 50% duty-cycle the divider shall be programmed as follows:
- even divider ratio => LOWTIME = HIGHTIME
EDGE =
0
- odd divider ratio => LOWTIME = HI 1
EDGE =
1
9.1.2.4 ARC_PLL_LOCK Register
31 2 1 0
Reserved ERROR LOCK
Address offset: 0x0110
Reset Value: 0x0000_0001
Access: R
Register for ARC PLL lock status
LOCK PLL lock indication
0
= PLL is unlocked
1
= PLL is locked
ERROR PLL error indication. Asserted high to to indicate that PLL was programmed
with an illegal value. PLL can be re-programmed once the ERROR status
bit is reset to
0